Lines Matching refs:RIU_WriteByte
148 #define RIU_WriteByte( u32Reg, u8Val ) \ macro
6207 …RIU_WriteByte( (((MS_U16)(VdDecTbl[u16Index*3])<<8)+VdDecTbl[u16Index*3+1]), (VdDecTbl[u16Index*3+… in HAL_AVD_WriteRegTbl()
6251 RIU_WriteByte(BK_AFEC_C2, 0xA5); in HAL_AVD_VDMCU_SoftStop()
6252 RIU_WriteByte(BK_AFEC_C0, 0xFA); in HAL_AVD_VDMCU_SoftStop()
6254 RIU_WriteByte(BK_AFEC_C2, 0x00); in HAL_AVD_VDMCU_SoftStop()
6255 RIU_WriteByte(BK_AFEC_C0, 0x00); in HAL_AVD_VDMCU_SoftStop()
6505 RIU_WriteByte(VD_MCU_ADDR_L, 0x00); in HAL_AVD_VDMCU_LoadDSP()
6506 RIU_WriteByte(VD_MCU_ADDR_H, 0x00); in HAL_AVD_VDMCU_LoadDSP()
6513 RIU_WriteByte(VD_MCU_SRAM_WD, pu8VD_DSP[u32I]); in HAL_AVD_VDMCU_LoadDSP()
6518 RIU_WriteByte(VD_MCU_ADDR_L, 0x00); in HAL_AVD_VDMCU_LoadDSP()
6519 RIU_WriteByte(VD_MCU_ADDR_H, 0x00); in HAL_AVD_VDMCU_LoadDSP()
6591 … RIU_WriteByte( astVdDecInitialize[i].u16Index, astVdDecInitialize[i].u8Value ); // write register in HAL_AVD_RegInit()
6654 RIU_WriteByte( BK_AFEC_04, 0x21 ); in HAL_AVD_AFEC_GetHWHsync()
6761 RIU_WriteByte(BK_AFEC_04, 0x04); in HAL_AVD_AFEC_GetNoiseMag()
6875 RIU_WriteByte(H_BK_ADC_ATOP(0x04), 0xB7); in HAL_AVD_AFEC_SetClockSource()
6876 RIU_WriteByte(L_BK_ADC_ATOP(0x04), 0xE0); in HAL_AVD_AFEC_SetClockSource()
6877 RIU_WriteByte(H_BK_ADC_ATOP(0x05), 0x07); in HAL_AVD_AFEC_SetClockSource()
6878 RIU_WriteByte(L_BK_ADC_ATOP(0x05), 0x3D); in HAL_AVD_AFEC_SetClockSource()
6879 RIU_WriteByte(H_BK_ADC_ATOP(0x06), 0xEB); in HAL_AVD_AFEC_SetClockSource()
6880 RIU_WriteByte(L_BK_ADC_ATOP(0x06), 0x7E); in HAL_AVD_AFEC_SetClockSource()
6881 RIU_WriteByte(H_BK_ADC_ATOP(0x5E), 0x1F); // new after T4 in HAL_AVD_AFEC_SetClockSource()
6891 RIU_WriteByte(0x3314L, 0x00); // Enable ADC clock in HAL_AVD_AFEC_SetClockSource()
6892 RIU_WriteByte(0x3315L, 0x01); in HAL_AVD_AFEC_SetClockSource()
6893 RIU_WriteByte(0x330AL, 0x00); // ADC_CLK in HAL_AVD_AFEC_SetClockSource()
6894 RIU_WriteByte(0x330BL, 0x00); in HAL_AVD_AFEC_SetClockSource()
6895 RIU_WriteByte(0x331AL, 0x04); // MPLLDIV10/2=43MHz in HAL_AVD_AFEC_SetClockSource()
6896 RIU_WriteByte(0x331BL, 0x04); // MPLLDIV10/2=43MHz in HAL_AVD_AFEC_SetClockSource()
6897 RIU_WriteByte(0x331CL, 0x00); // MPLLDIV10/2=43MHz in HAL_AVD_AFEC_SetClockSource()
6898 RIU_WriteByte(0x331DL, 0x00); // ADC_CLKOUT=144MHz in HAL_AVD_AFEC_SetClockSource()
6901 RIU_WriteByte(0x12002L, 0x04); // Enable VIF in HAL_AVD_AFEC_SetClockSource()
6902 RIU_WriteByte(0x12003L, 0x00); in HAL_AVD_AFEC_SetClockSource()
6905 RIU_WriteByte(0x1286AL, 0x04); // Reset MPLL in HAL_AVD_AFEC_SetClockSource()
6906 RIU_WriteByte(0x1286BL, 0x1E); in HAL_AVD_AFEC_SetClockSource()
6907 RIU_WriteByte(0x1286AL, 0x04); // Disable MPLL reset in HAL_AVD_AFEC_SetClockSource()
6908 RIU_WriteByte(0x1286BL, 0x06); in HAL_AVD_AFEC_SetClockSource()
6909 RIU_WriteByte(0x12869L, 0x00); // BY 20090715, ATSC will overwrite this value in HAL_AVD_AFEC_SetClockSource()
6910 RIU_WriteByte(0x12866L, 0x02); // Set MPLL_LOOP_DIV_FIRST and SECOND in HAL_AVD_AFEC_SetClockSource()
6911 RIU_WriteByte(0x12867L, 0x09); in HAL_AVD_AFEC_SetClockSource()
6912 RIU_WriteByte(0x12860L, 0x00); // Set MPLL_ADC_DIV_SEL in HAL_AVD_AFEC_SetClockSource()
6913 RIU_WriteByte(0x12861L, 0x06); in HAL_AVD_AFEC_SetClockSource()
6914 RIU_WriteByte(0x12802L, 0x1C); // Set IMUXS QMUXS in HAL_AVD_AFEC_SetClockSource()
6915 RIU_WriteByte(0x12803L, 0x11); in HAL_AVD_AFEC_SetClockSource()
6916 RIU_WriteByte(0x12818L, 0x00); // Set enable ADC clock in HAL_AVD_AFEC_SetClockSource()
6917 RIU_WriteByte(0x12819L, 0x00); in HAL_AVD_AFEC_SetClockSource()
6918 RIU_WriteByte(0x12840L, 0x60); // Disable PWDN_REF in HAL_AVD_AFEC_SetClockSource()
6919 RIU_WriteByte(0x12841L, 0x00); in HAL_AVD_AFEC_SetClockSource()
6920 RIU_WriteByte(0x12816L, 0x05); in HAL_AVD_AFEC_SetClockSource()
6921 RIU_WriteByte(0x12817L, 0x05); in HAL_AVD_AFEC_SetClockSource()
6924 RIU_WriteByte(0x12802L, 0x0C); in HAL_AVD_AFEC_SetClockSource()
6925 RIU_WriteByte(0x12803L, 0x10); in HAL_AVD_AFEC_SetClockSource()
6989 RIU_WriteByte (L_BK_ADC_ATOP(0x40), in HAL_AVD_AFEC_SetInput()
6992 RIU_WriteByte (L_BK_ADC_ATOP(0x42), 0xEC); // i.e. 0x83 in HAL_AVD_AFEC_SetInput()
6997 RIU_WriteByte (L_BK_ADC_ATOP(0x40), in HAL_AVD_AFEC_SetInput()
7000 RIU_WriteByte (L_BK_ADC_ATOP(0x42), 0xEC); // i.e. 0x83 in HAL_AVD_AFEC_SetInput()
7006 RIU_WriteByte (L_BK_ADC_ATOP(0x42), 0xEC); // i.e. 0x83 in HAL_AVD_AFEC_SetInput()
7023 RIU_WriteByte( BK_AFEC_1A, ( RIU_ReadByte( BK_AFEC_1A ) ) & ~0xC0 ); // disable SV input in HAL_AVD_AFEC_SetInput()
7026 RIU_WriteByte( BK_AFEC_7F, 0x65); // Switch to Comb Y/U/V 444 input. in HAL_AVD_AFEC_SetInput()
7043 RIU_WriteByte( BK_AFEC_1A, ( RIU_ReadByte( BK_AFEC_1A ) ) & ~0xC0 ); // disable SV input in HAL_AVD_AFEC_SetInput()
7046 RIU_WriteByte( BK_AFEC_7F, 0x65); // Switch to Comb Y/U/V 444 input. in HAL_AVD_AFEC_SetInput()
7065 RIU_WriteByte( BK_AFEC_1A, ( RIU_ReadByte(BK_AFEC_1A) )| 0xC0); // Enable SV input in HAL_AVD_AFEC_SetInput()
7068 … RIU_WriteByte( BK_AFEC_7F, 0x65); // Switch to Comb Y/U/V 444 input. <- 0x65 used in Saturn in HAL_AVD_AFEC_SetInput()
7084 RIU_WriteByte( BK_AFEC_1A, ( RIU_ReadByte( BK_AFEC_1A ) ) & ~0xC0 ); // disable SV input in HAL_AVD_AFEC_SetInput()
7087 RIU_WriteByte (H_BK_ADC_ATOP(0x44), 0xFF); // i.e. ATOP 0x88 in HAL_AVD_AFEC_SetInput()
7088 RIU_WriteByte (L_BK_ADC_ATOP(0x44), 0x10); // i.e. ATOP 0x87 in HAL_AVD_AFEC_SetInput()
7089 RIU_WriteByte (L_BK_ADC_ATOP(0x41), 0x18); // i.e. ATOP 0x81 in HAL_AVD_AFEC_SetInput()
7090 RIU_WriteByte (H_BK_ADC_ATOP(0x41), 0x40); // i.e. ATOP 0x82 in HAL_AVD_AFEC_SetInput()
7091 RIU_WriteByte (H_BK_ADC_ATOP(0x43), 0x2E); // i.e. ATOP 0x85 in HAL_AVD_AFEC_SetInput()
7092 RIU_WriteByte (L_BK_ADC_ATOP(0x43), 0x30); // i.e. ATOP 0x84 in HAL_AVD_AFEC_SetInput()
7094 RIU_WriteByte (L_BK_ADC_ATOP(0x1C), RIU_ReadByte(L_BK_ADC_ATOP(0x1C)) & 0xE0); in HAL_AVD_AFEC_SetInput()
7095 …RIU_WriteByte (L_BK_ADC_ATOP(0x2C), 0x00); // i.e. ATOP 0x58 set VClamp to VCLAMP_RGB_ClampGnd (i.… in HAL_AVD_AFEC_SetInput()
7096 RIU_WriteByte (H_BK_ADC_ATOP(0x1C), 0x40); // i.e. ATOP 0x37 in HAL_AVD_AFEC_SetInput()
7097 RIU_WriteByte (L_BK_ADC_ATOP(0x4C), 0xA1); // i.e. ATOP 0x98 in HAL_AVD_AFEC_SetInput()
7101 RIU_WriteByte (L_BK_ADC_DTOP(0x0B), 0xFF); // i.e. DTOP 0x14 set clamp placement in HAL_AVD_AFEC_SetInput()
7102 RIU_WriteByte (H_BK_ADC_DTOP(0x0B), 0x40); // i.e. DTOP 0x15 set clamp duration in HAL_AVD_AFEC_SetInput()
7103 RIU_WriteByte (L_BK_ADC_DTOP(0x07), 0x8A); // i.e. DTOP 0x0D in HAL_AVD_AFEC_SetInput()
7104 RIU_WriteByte (L_BK_ADC_DTOP(0x10), 0x00); // i.e. DTOP 0x20 in HAL_AVD_AFEC_SetInput()
7106 RIU_WriteByte(BK_AFEC_7F, 0x66); // Switch to Comb Y/U/V 444 input. in HAL_AVD_AFEC_SetInput()
7132 RIU_WriteByte(BK_AFEC_8F,0x3D); in HAL_AVD_AFEC_SetInput()
7133 RIU_WriteByte(BK_AFEC_20,0xBC); in HAL_AVD_AFEC_SetInput()
7134 RIU_WriteByte(BK_AFEC_21,0x1D); in HAL_AVD_AFEC_SetInput()
7142 RIU_WriteByte(BK_AFEC_8F,0x19); in HAL_AVD_AFEC_SetInput()
7143 RIU_WriteByte(BK_AFEC_20,0xB0); in HAL_AVD_AFEC_SetInput()
7144 RIU_WriteByte(BK_AFEC_21,0x19); in HAL_AVD_AFEC_SetInput()
7158 RIU_WriteByte(BK_AFEC_8F,0x19); in HAL_AVD_AFEC_SetInput()
7159 RIU_WriteByte(BK_AFEC_20,0xB0); in HAL_AVD_AFEC_SetInput()
7160 RIU_WriteByte(BK_AFEC_21,0x19); in HAL_AVD_AFEC_SetInput()
7241 RIU_WriteByte(BK_AFEC_A1, 0x6A); in HAL_AVD_AFEC_SetHTotal()
7242 RIU_WriteByte(BK_AFEC_A0, 0x3C); in HAL_AVD_AFEC_SetHTotal()
7252 RIU_WriteByte(BK_AFEC_9D, u32Mid >> 3); in HAL_AVD_AFEC_SetHTotal()
7253 RIU_WriteByte(BK_AFEC_9E, (MS_U8)(u32Mid &0x07) << 5); in HAL_AVD_AFEC_SetHTotal()
7256 RIU_WriteByte(BK_AFEC_9D, u32HTotal >> 3); in HAL_AVD_AFEC_SetHTotal()
7257 RIU_WriteByte(BK_AFEC_9E, (MS_U8)(u32HTotal & 0x07) << 5); in HAL_AVD_AFEC_SetHTotal()
7259 RIU_WriteByte(BK_AFEC_A1, u8A1Backup); in HAL_AVD_AFEC_SetHTotal()
7260 RIU_WriteByte(BK_AFEC_A0, u8A0Backup); in HAL_AVD_AFEC_SetHTotal()
7318 RIU_WriteByte(BK_AFEC_7B, u8BT656Width); // 656_HDES in HAL_AVD_AFEC_SetBT656Width()
7487 RIU_WriteByte (BK_AFEC_44, u8AgcFineGain); in HAL_AVD_AFEC_AGCSetFineGain()
7511 RIU_WriteByte (BK_AFEC_D7, u8ColorKillLevel); in HAL_AVD_AFEC_SetColorKillLevel()
7528 RIU_WriteByte (BK_AFEC_99, (eVDHsyncSensitivityTuning.u8DetectWinAfterLock & 0x0F) << 4 in HAL_AVD_AFEC_SetHsyncSensitivity()
7583 RIU_WriteByte(BK_AFEC_E3, u8Value); // decrease color stripe threshold for non-standard signals in HAL_AVD_AFEC_SetColorStripe()
7600 RIU_WriteByte(BK_COMB_E0,0xff); in HAL_AVD_COMB_Get3dCombTimingCheck()
7626 …RIU_WriteByte(BK_COMB_3F,(u32COMB_3D_Addr>> 4) & 0xFF); // <-<<< set 3D COMB BUF S… in HAL_AVD_COMB_SetMemoryProtect()
7627 …RIU_WriteByte(BK_COMB_3E,(u32COMB_3D_Addr >> 12) & 0xFF); // <-<<< set 3D COMB BUF S… in HAL_AVD_COMB_SetMemoryProtect()
7628 …RIU_WriteByte(BK_COMB_3D,(u32COMB_3D_Addr >> 20) & 0xFF); // <-<<< set 3D COMB BUF S… in HAL_AVD_COMB_SetMemoryProtect()
7629 …RIU_WriteByte(BK_COMB_67,(u32COMB_3D_Addr >> 28) & 0x03); // 20110721 Brian Add Com… in HAL_AVD_COMB_SetMemoryProtect()
7631 …RIU_WriteByte(BK_COMB_68,(u32COMB_3D_Addr+u32COMB_3D_Len) >> 28); // 20110721 Brian Add Com… in HAL_AVD_COMB_SetMemoryProtect()
7632 …RIU_WriteByte(BK_COMB_88,(u32COMB_3D_Addr+u32COMB_3D_Len) >> 20); // COMB memory protect add… in HAL_AVD_COMB_SetMemoryProtect()
7633 …RIU_WriteByte(BK_COMB_89,(u32COMB_3D_Addr+u32COMB_3D_Len) >> 12); // COMB memory protect add… in HAL_AVD_COMB_SetMemoryProtect()
7634 …RIU_WriteByte(BK_COMB_8A,(u32COMB_3D_Addr+u32COMB_3D_Len) >> 4); // COMB memory protect add… in HAL_AVD_COMB_SetMemoryProtect()
7723 RIU_WriteByte( BK_COMB_57, u8COMB57 ); in HAL_AVD_COMB_Set3dCombSpeed()
7724 RIU_WriteByte( BK_COMB_58, u8COMB58 ); in HAL_AVD_COMB_Set3dCombSpeed()
7742 RIU_WriteByte(BK_COMB_55, u8Threshold); in HAL_AVD_COMB_Set3dDetectionTolerance()
7762 RIU_WriteByte(BK_COMB_9F, 0xc8); in HAL_AVD_COMB_Set3dFineTune()
7763 RIU_WriteByte(BK_COMB_ED, 0x82); in HAL_AVD_COMB_Set3dFineTune()
7768 RIU_WriteByte(BK_COMB_9F, 0xc6); in HAL_AVD_COMB_Set3dFineTune()
7769 RIU_WriteByte(BK_COMB_ED, 0x80); in HAL_AVD_COMB_Set3dFineTune()
7787 RIU_WriteByte( BK_COMB_F2, u8Value ); in HAL_AVD_COMB_SetF2()
7815 RIU_WriteByte(BK_COMB_C0,0x60); in HAL_AVD_COMB_SetNonStandardFSC()
7828 RIU_WriteByte(BK_COMB_C0,0xA0); in HAL_AVD_COMB_SetNonStandardFSC()
7977 RIU_WriteByte( BK_COMB_5A, u8Tolerance); in HAL_AVD_COMB_SetHsyncTolerance()
8072 RIU_WriteByte( u16Addr ,u8Value); in HAL_AVD_SetReg()
8119 RIU_WriteByte(BK_AFEC_4F, 0x76); in HAL_AVD_AFEC_BackPorchWindowPosition()
8124 RIU_WriteByte(BK_AFEC_4F, 0x50); in HAL_AVD_AFEC_BackPorchWindowPosition()
8129 RIU_WriteByte(BK_AFEC_4F, u8Value); in HAL_AVD_AFEC_BackPorchWindowPosition()
8177 RIU_WriteByte(BK_AFEC_80, 0x17); in HAL_AVD_ShiftClk()
8178 RIU_WriteByte(BK_AFEC_81, 0x77); in HAL_AVD_ShiftClk()
8179 RIU_WriteByte(BK_AFEC_82, 0x78); in HAL_AVD_ShiftClk()
8180 RIU_WriteByte(BK_AFEC_8F, 0x0D); in HAL_AVD_ShiftClk()
8183 RIU_WriteByte(BK_AFEC_80, 0x12); in HAL_AVD_ShiftClk()
8184 RIU_WriteByte(BK_AFEC_81, 0xF2); in HAL_AVD_ShiftClk()
8185 RIU_WriteByte(BK_AFEC_82, 0x37); in HAL_AVD_ShiftClk()
8186 RIU_WriteByte(BK_AFEC_8F, 0x0D); in HAL_AVD_ShiftClk()
8189 RIU_WriteByte(BK_AFEC_80, 0x17); in HAL_AVD_ShiftClk()
8190 RIU_WriteByte(BK_AFEC_81, 0x7E); in HAL_AVD_ShiftClk()
8191 RIU_WriteByte(BK_AFEC_82, 0x13); in HAL_AVD_ShiftClk()
8192 RIU_WriteByte(BK_AFEC_8F, 0x0D); in HAL_AVD_ShiftClk()
8195 RIU_WriteByte(BK_AFEC_80, 0x17); in HAL_AVD_ShiftClk()
8196 RIU_WriteByte(BK_AFEC_81, 0x73); in HAL_AVD_ShiftClk()
8197 RIU_WriteByte(BK_AFEC_82, 0x41); in HAL_AVD_ShiftClk()
8198 RIU_WriteByte(BK_AFEC_8F, 0x0D); in HAL_AVD_ShiftClk()
8201 RIU_WriteByte(BK_AFEC_80, 0x13); in HAL_AVD_ShiftClk()
8202 RIU_WriteByte(BK_AFEC_81, 0x9A); in HAL_AVD_ShiftClk()
8203 RIU_WriteByte(BK_AFEC_82, 0x41); in HAL_AVD_ShiftClk()
8204 RIU_WriteByte(BK_AFEC_8F, 0x0D); in HAL_AVD_ShiftClk()
8207 RIU_WriteByte(BK_AFEC_80, 0x12); in HAL_AVD_ShiftClk()
8208 RIU_WriteByte(BK_AFEC_81, 0xF2); in HAL_AVD_ShiftClk()
8209 RIU_WriteByte(BK_AFEC_82, 0x37); in HAL_AVD_ShiftClk()
8210 RIU_WriteByte(BK_AFEC_8F, 0x0D); in HAL_AVD_ShiftClk()
8219 RIU_WriteByte(BK_AFEC_80, 0x18); in HAL_AVD_ShiftClk()
8220 RIU_WriteByte(BK_AFEC_81, 0xCE); in HAL_AVD_ShiftClk()
8221 RIU_WriteByte(BK_AFEC_82, 0xC0); in HAL_AVD_ShiftClk()
8222 RIU_WriteByte(BK_AFEC_8F, 0x0D); in HAL_AVD_ShiftClk()
8225 RIU_WriteByte(BK_AFEC_80, 0x14); in HAL_AVD_ShiftClk()
8226 RIU_WriteByte(BK_AFEC_81, 0x07); in HAL_AVD_ShiftClk()
8227 RIU_WriteByte(BK_AFEC_82, 0x5F); in HAL_AVD_ShiftClk()
8228 RIU_WriteByte(BK_AFEC_8F, 0x0D); in HAL_AVD_ShiftClk()
8231 RIU_WriteByte(BK_AFEC_80, 0x18); in HAL_AVD_ShiftClk()
8232 RIU_WriteByte(BK_AFEC_81, 0xD5); in HAL_AVD_ShiftClk()
8233 RIU_WriteByte(BK_AFEC_82, 0xBD); in HAL_AVD_ShiftClk()
8234 RIU_WriteByte(BK_AFEC_8F, 0x0D); in HAL_AVD_ShiftClk()
8237 RIU_WriteByte(BK_AFEC_80, 0x18); in HAL_AVD_ShiftClk()
8238 RIU_WriteByte(BK_AFEC_81, 0xCA); in HAL_AVD_ShiftClk()
8239 RIU_WriteByte(BK_AFEC_82, 0x4D); in HAL_AVD_ShiftClk()
8240 RIU_WriteByte(BK_AFEC_8F, 0x0D); in HAL_AVD_ShiftClk()
8243 RIU_WriteByte(BK_AFEC_80, 0x14); in HAL_AVD_ShiftClk()
8244 RIU_WriteByte(BK_AFEC_81, 0xB9); in HAL_AVD_ShiftClk()
8245 RIU_WriteByte(BK_AFEC_82, 0x03); in HAL_AVD_ShiftClk()
8246 RIU_WriteByte(BK_AFEC_8F, 0x0D); in HAL_AVD_ShiftClk()
8249 RIU_WriteByte(BK_AFEC_80, 0x14); in HAL_AVD_ShiftClk()
8250 RIU_WriteByte(BK_AFEC_81, 0x07); in HAL_AVD_ShiftClk()
8251 RIU_WriteByte(BK_AFEC_82, 0x5F); in HAL_AVD_ShiftClk()
8252 RIU_WriteByte(BK_AFEC_8F, 0x0D); in HAL_AVD_ShiftClk()
8260 RIU_WriteByte(BK_AFEC_8F, 0x3D); in HAL_AVD_ShiftClk()
8264 RIU_WriteByte(BK_AFEC_8F, 0x1D); //AFEC_8F[4]=1, use HW mode default is 43.2Mz in HAL_AVD_ShiftClk()