Lines Matching refs:RIU_WriteByte
148 #define RIU_WriteByte( u32Reg, u8Val ) \ macro
2862 …RIU_WriteByte( (((MS_U16)(VdDecTbl[u16Index*3])<<8)+VdDecTbl[u16Index*3+1]), (VdDecTbl[u16Index*3+… in HAL_AVD_WriteRegTbl()
2906 RIU_WriteByte(BK_AFEC_C2, 0xA5); in HAL_AVD_VDMCU_SoftStop()
2907 RIU_WriteByte(BK_AFEC_C0, 0xFA); in HAL_AVD_VDMCU_SoftStop()
2909 RIU_WriteByte(BK_AFEC_C2, 0x00); in HAL_AVD_VDMCU_SoftStop()
2910 RIU_WriteByte(BK_AFEC_C0, 0x00); in HAL_AVD_VDMCU_SoftStop()
3137 RIU_WriteByte(VD_MCU_ADDR_L, 0x00); in HAL_AVD_VDMCU_LoadDSP()
3138 RIU_WriteByte(VD_MCU_ADDR_H, 0x00); in HAL_AVD_VDMCU_LoadDSP()
3145 RIU_WriteByte(VD_MCU_SRAM_WD, pu8VD_DSP[u32I]); in HAL_AVD_VDMCU_LoadDSP()
3150 RIU_WriteByte(VD_MCU_ADDR_L, 0x00); in HAL_AVD_VDMCU_LoadDSP()
3151 RIU_WriteByte(VD_MCU_ADDR_H, 0x00); in HAL_AVD_VDMCU_LoadDSP()
3234 … RIU_WriteByte( astVdDecInitialize[i].u16Index, astVdDecInitialize[i].u8Value ); // write register in HAL_AVD_RegInit()
3297 RIU_WriteByte( BK_AFEC_04, 0x21 ); in HAL_AVD_AFEC_GetHWHsync()
3404 RIU_WriteByte(BK_AFEC_04, 0x04); in HAL_AVD_AFEC_GetNoiseMag()
3518 RIU_WriteByte(H_BK_ADC_ATOP(0x04), 0xB7); in HAL_AVD_AFEC_SetClockSource()
3519 RIU_WriteByte(L_BK_ADC_ATOP(0x04), 0xE0); in HAL_AVD_AFEC_SetClockSource()
3520 RIU_WriteByte(H_BK_ADC_ATOP(0x05), 0x07); in HAL_AVD_AFEC_SetClockSource()
3521 RIU_WriteByte(L_BK_ADC_ATOP(0x05), 0x3D); in HAL_AVD_AFEC_SetClockSource()
3522 RIU_WriteByte(H_BK_ADC_ATOP(0x06), 0xEB); in HAL_AVD_AFEC_SetClockSource()
3523 RIU_WriteByte(L_BK_ADC_ATOP(0x06), 0x7E); in HAL_AVD_AFEC_SetClockSource()
3524 RIU_WriteByte(H_BK_ADC_ATOP(0x5E), 0x1F); // new after T4 in HAL_AVD_AFEC_SetClockSource()
3534 RIU_WriteByte(0x3314L, 0x00); // Enable ADC clock in HAL_AVD_AFEC_SetClockSource()
3535 RIU_WriteByte(0x3315L, 0x01); in HAL_AVD_AFEC_SetClockSource()
3536 RIU_WriteByte(0x330AL, 0x00); // ADC_CLK in HAL_AVD_AFEC_SetClockSource()
3537 RIU_WriteByte(0x330BL, 0x00); in HAL_AVD_AFEC_SetClockSource()
3538 RIU_WriteByte(0x331AL, 0x04); // MPLLDIV10/2=43MHz in HAL_AVD_AFEC_SetClockSource()
3539 RIU_WriteByte(0x331BL, 0x04); // MPLLDIV10/2=43MHz in HAL_AVD_AFEC_SetClockSource()
3540 RIU_WriteByte(0x331CL, 0x00); // MPLLDIV10/2=43MHz in HAL_AVD_AFEC_SetClockSource()
3541 RIU_WriteByte(0x331DL, 0x00); // ADC_CLKOUT=144MHz in HAL_AVD_AFEC_SetClockSource()
3544 RIU_WriteByte(0x12002L, 0x04); // Enable VIF in HAL_AVD_AFEC_SetClockSource()
3545 RIU_WriteByte(0x12003L, 0x00); in HAL_AVD_AFEC_SetClockSource()
3548 RIU_WriteByte(0x1286AL, 0x04); // Reset MPLL in HAL_AVD_AFEC_SetClockSource()
3549 RIU_WriteByte(0x1286BL, 0x1E); in HAL_AVD_AFEC_SetClockSource()
3550 RIU_WriteByte(0x1286AL, 0x04); // Disable MPLL reset in HAL_AVD_AFEC_SetClockSource()
3551 RIU_WriteByte(0x1286BL, 0x06); in HAL_AVD_AFEC_SetClockSource()
3552 RIU_WriteByte(0x12869L, 0x00); // BY 20090715, ATSC will overwrite this value in HAL_AVD_AFEC_SetClockSource()
3553 RIU_WriteByte(0x12866L, 0x02); // Set MPLL_LOOP_DIV_FIRST and SECOND in HAL_AVD_AFEC_SetClockSource()
3554 RIU_WriteByte(0x12867L, 0x09); in HAL_AVD_AFEC_SetClockSource()
3555 RIU_WriteByte(0x12860L, 0x00); // Set MPLL_ADC_DIV_SEL in HAL_AVD_AFEC_SetClockSource()
3556 RIU_WriteByte(0x12861L, 0x06); in HAL_AVD_AFEC_SetClockSource()
3557 RIU_WriteByte(0x12802L, 0x1C); // Set IMUXS QMUXS in HAL_AVD_AFEC_SetClockSource()
3558 RIU_WriteByte(0x12803L, 0x11); in HAL_AVD_AFEC_SetClockSource()
3559 RIU_WriteByte(0x12818L, 0x00); // Set enable ADC clock in HAL_AVD_AFEC_SetClockSource()
3560 RIU_WriteByte(0x12819L, 0x00); in HAL_AVD_AFEC_SetClockSource()
3561 RIU_WriteByte(0x12840L, 0x60); // Disable PWDN_REF in HAL_AVD_AFEC_SetClockSource()
3562 RIU_WriteByte(0x12841L, 0x00); in HAL_AVD_AFEC_SetClockSource()
3563 RIU_WriteByte(0x12816L, 0x05); in HAL_AVD_AFEC_SetClockSource()
3564 RIU_WriteByte(0x12817L, 0x05); in HAL_AVD_AFEC_SetClockSource()
3567 RIU_WriteByte(0x12802L, 0x0C); in HAL_AVD_AFEC_SetClockSource()
3568 RIU_WriteByte(0x12803L, 0x10); in HAL_AVD_AFEC_SetClockSource()
3626 RIU_WriteByte (L_BK_ADC_ATOP(0x40), in HAL_AVD_AFEC_SetInput()
3629 RIU_WriteByte (L_BK_ADC_ATOP(0x42), 0xEC); // i.e. 0x83 in HAL_AVD_AFEC_SetInput()
3634 RIU_WriteByte (L_BK_ADC_ATOP(0x40), in HAL_AVD_AFEC_SetInput()
3637 RIU_WriteByte (L_BK_ADC_ATOP(0x42), 0xEC); // i.e. 0x83 in HAL_AVD_AFEC_SetInput()
3643 RIU_WriteByte (L_BK_ADC_ATOP(0x42), 0xEC); // i.e. 0x83 in HAL_AVD_AFEC_SetInput()
3660 RIU_WriteByte( BK_AFEC_1A, ( RIU_ReadByte( BK_AFEC_1A ) ) & ~0xC0 ); // disable SV input in HAL_AVD_AFEC_SetInput()
3663 RIU_WriteByte( BK_AFEC_7F, 0x65); // Switch to Comb Y/U/V 444 input. in HAL_AVD_AFEC_SetInput()
3680 RIU_WriteByte( BK_AFEC_1A, ( RIU_ReadByte( BK_AFEC_1A ) ) & ~0xC0 ); // disable SV input in HAL_AVD_AFEC_SetInput()
3683 RIU_WriteByte( BK_AFEC_7F, 0x65); // Switch to Comb Y/U/V 444 input. in HAL_AVD_AFEC_SetInput()
3702 RIU_WriteByte( BK_AFEC_1A, ( RIU_ReadByte(BK_AFEC_1A) )| 0xC0); // Enable SV input in HAL_AVD_AFEC_SetInput()
3705 … RIU_WriteByte( BK_AFEC_7F, 0x65); // Switch to Comb Y/U/V 444 input. <- 0x65 used in Saturn in HAL_AVD_AFEC_SetInput()
3721 RIU_WriteByte( BK_AFEC_1A, ( RIU_ReadByte( BK_AFEC_1A ) ) & ~0xC0 ); // disable SV input in HAL_AVD_AFEC_SetInput()
3724 RIU_WriteByte (H_BK_ADC_ATOP(0x44), 0xFF); // i.e. ATOP 0x88 in HAL_AVD_AFEC_SetInput()
3725 RIU_WriteByte (L_BK_ADC_ATOP(0x44), 0x10); // i.e. ATOP 0x87 in HAL_AVD_AFEC_SetInput()
3726 RIU_WriteByte (L_BK_ADC_ATOP(0x41), 0x18); // i.e. ATOP 0x81 in HAL_AVD_AFEC_SetInput()
3727 RIU_WriteByte (H_BK_ADC_ATOP(0x41), 0x40); // i.e. ATOP 0x82 in HAL_AVD_AFEC_SetInput()
3728 RIU_WriteByte (H_BK_ADC_ATOP(0x43), 0x2E); // i.e. ATOP 0x85 in HAL_AVD_AFEC_SetInput()
3729 RIU_WriteByte (L_BK_ADC_ATOP(0x43), 0x30); // i.e. ATOP 0x84 in HAL_AVD_AFEC_SetInput()
3731 RIU_WriteByte (L_BK_ADC_ATOP(0x1C), RIU_ReadByte(L_BK_ADC_ATOP(0x1C)) & 0xE0); in HAL_AVD_AFEC_SetInput()
3732 …RIU_WriteByte (L_BK_ADC_ATOP(0x2C), 0x00); // i.e. ATOP 0x58 set VClamp to VCLAMP_RGB_ClampGnd (i.… in HAL_AVD_AFEC_SetInput()
3733 RIU_WriteByte (H_BK_ADC_ATOP(0x1C), 0x40); // i.e. ATOP 0x37 in HAL_AVD_AFEC_SetInput()
3734 RIU_WriteByte (L_BK_ADC_ATOP(0x4C), 0xA1); // i.e. ATOP 0x98 in HAL_AVD_AFEC_SetInput()
3738 RIU_WriteByte (L_BK_ADC_DTOP(0x0B), 0xFF); // i.e. DTOP 0x14 set clamp placement in HAL_AVD_AFEC_SetInput()
3739 RIU_WriteByte (H_BK_ADC_DTOP(0x0B), 0x40); // i.e. DTOP 0x15 set clamp duration in HAL_AVD_AFEC_SetInput()
3740 RIU_WriteByte (L_BK_ADC_DTOP(0x07), 0x8A); // i.e. DTOP 0x0D in HAL_AVD_AFEC_SetInput()
3741 RIU_WriteByte (L_BK_ADC_DTOP(0x10), 0x00); // i.e. DTOP 0x20 in HAL_AVD_AFEC_SetInput()
3743 RIU_WriteByte(BK_AFEC_7F, 0x66); // Switch to Comb Y/U/V 444 input. in HAL_AVD_AFEC_SetInput()
3769 RIU_WriteByte(BK_AFEC_8F,0x3D); in HAL_AVD_AFEC_SetInput()
3770 RIU_WriteByte(BK_AFEC_20,0xBC); in HAL_AVD_AFEC_SetInput()
3771 RIU_WriteByte(BK_AFEC_21,0x1D); in HAL_AVD_AFEC_SetInput()
3779 RIU_WriteByte(BK_AFEC_8F,0x19); in HAL_AVD_AFEC_SetInput()
3780 RIU_WriteByte(BK_AFEC_20,0xB0); in HAL_AVD_AFEC_SetInput()
3781 RIU_WriteByte(BK_AFEC_21,0x19); in HAL_AVD_AFEC_SetInput()
3795 RIU_WriteByte(BK_AFEC_8F,0x19); in HAL_AVD_AFEC_SetInput()
3796 RIU_WriteByte(BK_AFEC_20,0xB0); in HAL_AVD_AFEC_SetInput()
3797 RIU_WriteByte(BK_AFEC_21,0x19); in HAL_AVD_AFEC_SetInput()
3878 RIU_WriteByte(BK_AFEC_A1, 0x6A); in HAL_AVD_AFEC_SetHTotal()
3879 RIU_WriteByte(BK_AFEC_A0, 0x3C); in HAL_AVD_AFEC_SetHTotal()
3889 RIU_WriteByte(BK_AFEC_9D, u32Mid >> 3); in HAL_AVD_AFEC_SetHTotal()
3890 RIU_WriteByte(BK_AFEC_9E, (MS_U8)(u32Mid &0x07) << 5); in HAL_AVD_AFEC_SetHTotal()
3893 RIU_WriteByte(BK_AFEC_9D, u32HTotal >> 3); in HAL_AVD_AFEC_SetHTotal()
3894 RIU_WriteByte(BK_AFEC_9E, (MS_U8)(u32HTotal & 0x07) << 5); in HAL_AVD_AFEC_SetHTotal()
3896 RIU_WriteByte(BK_AFEC_A1, u8A1Backup); in HAL_AVD_AFEC_SetHTotal()
3897 RIU_WriteByte(BK_AFEC_A0, u8A0Backup); in HAL_AVD_AFEC_SetHTotal()
3955 RIU_WriteByte(BK_AFEC_7B, u8BT656Width); // 656_HDES in HAL_AVD_AFEC_SetBT656Width()
4124 RIU_WriteByte (BK_AFEC_44, u8AgcFineGain); in HAL_AVD_AFEC_AGCSetFineGain()
4148 RIU_WriteByte (BK_AFEC_D7, u8ColorKillLevel); in HAL_AVD_AFEC_SetColorKillLevel()
4165 RIU_WriteByte (BK_AFEC_99, (eVDHsyncSensitivityTuning.u8DetectWinAfterLock & 0x0F) << 4 in HAL_AVD_AFEC_SetHsyncSensitivity()
4220 RIU_WriteByte(BK_AFEC_E3, u8Value); // decrease color stripe threshold for non-standard signals in HAL_AVD_AFEC_SetColorStripe()
4237 RIU_WriteByte(BK_COMB_E0,0xff); in HAL_AVD_COMB_Get3dCombTimingCheck()
4263 …RIU_WriteByte(BK_COMB_3F,(u32COMB_3D_Addr>> 4) & 0xFF); // <-<<< set 3D COMB BUF S… in HAL_AVD_COMB_SetMemoryProtect()
4264 …RIU_WriteByte(BK_COMB_3E,(u32COMB_3D_Addr >> 12) & 0xFF); // <-<<< set 3D COMB BUF S… in HAL_AVD_COMB_SetMemoryProtect()
4265 …RIU_WriteByte(BK_COMB_3D,(u32COMB_3D_Addr >> 20) & 0xFF); // <-<<< set 3D COMB BUF S… in HAL_AVD_COMB_SetMemoryProtect()
4266 …RIU_WriteByte(BK_COMB_67,(u32COMB_3D_Addr >> 28) & 0x07); // 20141104 Dia Add Comb_6… in HAL_AVD_COMB_SetMemoryProtect()
4268 …RIU_WriteByte(BK_COMB_68,(u32COMB_3D_Addr+u32COMB_3D_Len) >> 28); // 20110721 Brian Add Com… in HAL_AVD_COMB_SetMemoryProtect()
4269 …RIU_WriteByte(BK_COMB_88,(u32COMB_3D_Addr+u32COMB_3D_Len) >> 20); // COMB memory protect add… in HAL_AVD_COMB_SetMemoryProtect()
4270 …RIU_WriteByte(BK_COMB_89,(u32COMB_3D_Addr+u32COMB_3D_Len) >> 12); // COMB memory protect add… in HAL_AVD_COMB_SetMemoryProtect()
4271 …RIU_WriteByte(BK_COMB_8A,(u32COMB_3D_Addr+u32COMB_3D_Len) >> 4); // COMB memory protect add… in HAL_AVD_COMB_SetMemoryProtect()
4360 RIU_WriteByte( BK_COMB_57, u8COMB57 ); in HAL_AVD_COMB_Set3dCombSpeed()
4361 RIU_WriteByte( BK_COMB_58, u8COMB58 ); in HAL_AVD_COMB_Set3dCombSpeed()
4379 RIU_WriteByte(BK_COMB_55, u8Threshold); in HAL_AVD_COMB_Set3dDetectionTolerance()
4399 RIU_WriteByte(BK_COMB_9F, 0xc8); in HAL_AVD_COMB_Set3dFineTune()
4400 RIU_WriteByte(BK_COMB_ED, 0x82); in HAL_AVD_COMB_Set3dFineTune()
4405 RIU_WriteByte(BK_COMB_9F, 0xc6); in HAL_AVD_COMB_Set3dFineTune()
4406 RIU_WriteByte(BK_COMB_ED, 0x80); in HAL_AVD_COMB_Set3dFineTune()
4424 RIU_WriteByte( BK_COMB_F2, u8Value ); in HAL_AVD_COMB_SetF2()
4452 RIU_WriteByte(BK_COMB_C0,0x60); in HAL_AVD_COMB_SetNonStandardFSC()
4465 RIU_WriteByte(BK_COMB_C0,0xA0); in HAL_AVD_COMB_SetNonStandardFSC()
4614 RIU_WriteByte( BK_COMB_5A, u8Tolerance); in HAL_AVD_COMB_SetHsyncTolerance()
4709 RIU_WriteByte( u16Addr ,u8Value); in HAL_AVD_SetReg()
4756 RIU_WriteByte(BK_AFEC_4F, 0x76); in HAL_AVD_AFEC_BackPorchWindowPosition()
4761 RIU_WriteByte(BK_AFEC_4F, 0x50); in HAL_AVD_AFEC_BackPorchWindowPosition()
4766 RIU_WriteByte(BK_AFEC_4F, u8Value); in HAL_AVD_AFEC_BackPorchWindowPosition()
4796 RIU_WriteByte(BK_AFEC_80, 0x17); in HAL_AVD_ShiftClk()
4797 RIU_WriteByte(BK_AFEC_81, 0x77); in HAL_AVD_ShiftClk()
4798 RIU_WriteByte(BK_AFEC_82, 0x78); in HAL_AVD_ShiftClk()
4799 RIU_WriteByte(BK_AFEC_8F, 0x0D); in HAL_AVD_ShiftClk()
4802 RIU_WriteByte(BK_AFEC_80, 0x12); in HAL_AVD_ShiftClk()
4803 RIU_WriteByte(BK_AFEC_81, 0xF2); in HAL_AVD_ShiftClk()
4804 RIU_WriteByte(BK_AFEC_82, 0x37); in HAL_AVD_ShiftClk()
4805 RIU_WriteByte(BK_AFEC_8F, 0x0D); in HAL_AVD_ShiftClk()
4808 RIU_WriteByte(BK_AFEC_80, 0x17); in HAL_AVD_ShiftClk()
4809 RIU_WriteByte(BK_AFEC_81, 0x7E); in HAL_AVD_ShiftClk()
4810 RIU_WriteByte(BK_AFEC_82, 0x13); in HAL_AVD_ShiftClk()
4811 RIU_WriteByte(BK_AFEC_8F, 0x0D); in HAL_AVD_ShiftClk()
4814 RIU_WriteByte(BK_AFEC_80, 0x17); in HAL_AVD_ShiftClk()
4815 RIU_WriteByte(BK_AFEC_81, 0x73); in HAL_AVD_ShiftClk()
4816 RIU_WriteByte(BK_AFEC_82, 0x41); in HAL_AVD_ShiftClk()
4817 RIU_WriteByte(BK_AFEC_8F, 0x0D); in HAL_AVD_ShiftClk()
4820 RIU_WriteByte(BK_AFEC_80, 0x13); in HAL_AVD_ShiftClk()
4821 RIU_WriteByte(BK_AFEC_81, 0x9A); in HAL_AVD_ShiftClk()
4822 RIU_WriteByte(BK_AFEC_82, 0x41); in HAL_AVD_ShiftClk()
4823 RIU_WriteByte(BK_AFEC_8F, 0x0D); in HAL_AVD_ShiftClk()
4826 RIU_WriteByte(BK_AFEC_80, 0x12); in HAL_AVD_ShiftClk()
4827 RIU_WriteByte(BK_AFEC_81, 0xF2); in HAL_AVD_ShiftClk()
4828 RIU_WriteByte(BK_AFEC_82, 0x37); in HAL_AVD_ShiftClk()
4829 RIU_WriteByte(BK_AFEC_8F, 0x0D); in HAL_AVD_ShiftClk()
4838 RIU_WriteByte(BK_AFEC_80, 0x18); in HAL_AVD_ShiftClk()
4839 RIU_WriteByte(BK_AFEC_81, 0xCE); in HAL_AVD_ShiftClk()
4840 RIU_WriteByte(BK_AFEC_82, 0xC0); in HAL_AVD_ShiftClk()
4841 RIU_WriteByte(BK_AFEC_8F, 0x0D); in HAL_AVD_ShiftClk()
4844 RIU_WriteByte(BK_AFEC_80, 0x14); in HAL_AVD_ShiftClk()
4845 RIU_WriteByte(BK_AFEC_81, 0x07); in HAL_AVD_ShiftClk()
4846 RIU_WriteByte(BK_AFEC_82, 0x5F); in HAL_AVD_ShiftClk()
4847 RIU_WriteByte(BK_AFEC_8F, 0x0D); in HAL_AVD_ShiftClk()
4850 RIU_WriteByte(BK_AFEC_80, 0x18); in HAL_AVD_ShiftClk()
4851 RIU_WriteByte(BK_AFEC_81, 0xD5); in HAL_AVD_ShiftClk()
4852 RIU_WriteByte(BK_AFEC_82, 0xBD); in HAL_AVD_ShiftClk()
4853 RIU_WriteByte(BK_AFEC_8F, 0x0D); in HAL_AVD_ShiftClk()
4856 RIU_WriteByte(BK_AFEC_80, 0x18); in HAL_AVD_ShiftClk()
4857 RIU_WriteByte(BK_AFEC_81, 0xCA); in HAL_AVD_ShiftClk()
4858 RIU_WriteByte(BK_AFEC_82, 0x4D); in HAL_AVD_ShiftClk()
4859 RIU_WriteByte(BK_AFEC_8F, 0x0D); in HAL_AVD_ShiftClk()
4862 RIU_WriteByte(BK_AFEC_80, 0x14); in HAL_AVD_ShiftClk()
4863 RIU_WriteByte(BK_AFEC_81, 0xB9); in HAL_AVD_ShiftClk()
4864 RIU_WriteByte(BK_AFEC_82, 0x03); in HAL_AVD_ShiftClk()
4865 RIU_WriteByte(BK_AFEC_8F, 0x0D); in HAL_AVD_ShiftClk()
4868 RIU_WriteByte(BK_AFEC_80, 0x14); in HAL_AVD_ShiftClk()
4869 RIU_WriteByte(BK_AFEC_81, 0x07); in HAL_AVD_ShiftClk()
4870 RIU_WriteByte(BK_AFEC_82, 0x5F); in HAL_AVD_ShiftClk()
4871 RIU_WriteByte(BK_AFEC_8F, 0x0D); in HAL_AVD_ShiftClk()
4879 RIU_WriteByte(BK_AFEC_8F, 0x3D); in HAL_AVD_ShiftClk()
4883 RIU_WriteByte(BK_AFEC_8F, 0x1D); //AFEC_8F[4]=1, use HW mode default is 43.2Mz in HAL_AVD_ShiftClk()