Lines Matching refs:DISABLE
3014 HAL_AVD_VDMCU_SetFreeze(DISABLE); in HAL_AVD_VDMCU_SetClock()
3072 HAL_AVD_VDMCU_SetFreeze(DISABLE); in HAL_AVD_VDMCU_SetClock()
3128 RIU_WriteRegBit(VD_MCU_SRAM_EN, DISABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
3167 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, DISABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
3176 HAL_AVD_VDMCU_SetFreeze(DISABLE); in HAL_AVD_VDMCU_LoadDSP()
3215 RIU_WriteRegBit(BK_AFEC_14, DISABLE, BIT(7)); in HAL_AVD_RegInit()
3433 RIU_WriteRegBit(BK_AFEC_16, DISABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
3438 HAL_AVD_VDMCU_SetFreeze(DISABLE); in HAL_AVD_AFEC_McuReset()
3483 RIU_WriteRegBit (L_BK_CLKGEN0(0x21), DISABLE, BIT(0)); // CLK_VDMCU, 0:Enable 1:Disable in HAL_AVD_AFEC_SetClock()
3506 RIU_WriteRegBit(L_BK_CLKGEN0(0x00), DISABLE, BIT(4)); in HAL_AVD_AFEC_SetClockSource()
3656 RIU_WriteRegBit (BK_COMB_10, DISABLE, BIT(7)); // <- SET COMB in HAL_AVD_AFEC_SetInput()
3661 RIU_WriteRegBit( BK_AFEC_1F, DISABLE, BIT(7)); // disable clamp C in HAL_AVD_AFEC_SetInput()
3676 RIU_WriteRegBit (BK_COMB_10, DISABLE, BIT(7)); // <- SET COMB in HAL_AVD_AFEC_SetInput()
3681 RIU_WriteRegBit( BK_AFEC_1F, DISABLE, BIT(7)); // disable clamp C in HAL_AVD_AFEC_SetInput()
3690 HAL_AVD_COMB_Set3dCombMid(DISABLE); in HAL_AVD_AFEC_SetInput()
3717 RIU_WriteRegBit (BK_COMB_10, DISABLE, BIT(7)); // <- SET COMB in HAL_AVD_AFEC_SetInput()
3722 RIU_WriteRegBit( BK_AFEC_1F, DISABLE, BIT(7)); // disable clamp C in HAL_AVD_AFEC_SetInput()
3760 RIU_WriteRegBit(BK_AFEC_8F,DISABLE,BIT(5)); in HAL_AVD_AFEC_SetInput()
3775 RIU_WriteRegBit(BK_AFEC_CF,DISABLE,BIT(7)); in HAL_AVD_AFEC_SetInput()
3776 RIU_WriteRegBit(H_BK_CHIPTOP(0x13), DISABLE, BIT(8)); //20090611EL in HAL_AVD_AFEC_SetInput()
3777 …RIU_WriteRegBit(BK_AFEC_40,DISABLE,BIT(4)); // BY 20090630 put gain setting temporarily, TODO move… in HAL_AVD_AFEC_SetInput()
3778 RIU_WriteRegBit(BK_AFEC_40,DISABLE,BIT(7)); // disable VIF in hardware in HAL_AVD_AFEC_SetInput()
3786 HAL_AVD_AFEC_EnableCVBSLPF(DISABLE); in HAL_AVD_AFEC_SetInput()
3787 RIU_WriteRegBit(BK_AFEC_8F,DISABLE,BIT(5)); in HAL_AVD_AFEC_SetInput()
3791 RIU_WriteRegBit(BK_AFEC_CF,DISABLE,BIT(7)); in HAL_AVD_AFEC_SetInput()
3792 RIU_WriteRegBit(H_BK_CHIPTOP(0x13), DISABLE, BIT(8)); //20090611EL in HAL_AVD_AFEC_SetInput()
3793 …RIU_WriteRegBit(BK_AFEC_40,DISABLE,BIT(4)); // BY 20090630 put gain setting temporarily, TODO move… in HAL_AVD_AFEC_SetInput()
3794 RIU_WriteRegBit(BK_AFEC_40,DISABLE,BIT(7)); // disable VIF in hardware in HAL_AVD_AFEC_SetInput()
3899 RIU_WriteRegBit(BK_AFEC_A0, DISABLE, BIT(7)); in HAL_AVD_AFEC_SetHTotal()
3903 RIU_WriteRegBit(BK_COMB_50, DISABLE, BIT(0)); in HAL_AVD_AFEC_SetHTotal()
3998 HAL_AVD_AFEC_Set656DCOffset(DISABLE); in HAL_AVD_AFEC_SetFSCMode()
4004 HAL_AVD_COMB_Set3dCombMid(DISABLE); in HAL_AVD_AFEC_SetFSCMode()
4086 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetMode()
4107 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetCoarseGain()
4128 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetFineGain()
4297 RIU_WriteRegBit(BK_COMB_EE, DISABLE, BIT(7)); in HAL_AVD_COMB_Set3dCombMid()
4298 RIU_WriteRegBit(BK_COMB_2D, DISABLE, BIT(4)); in HAL_AVD_COMB_Set3dCombMid()
4331 … RIU_WriteRegBit( BK_COMB_2D, DISABLE, BIT(4)); // T3 Transition Vertical line in channel change. in HAL_AVD_COMB_Set3dComb()
4333 HAL_AVD_COMB_Set3dCombMid(DISABLE); in HAL_AVD_COMB_Set3dComb()
4556 HAL_AVD_COMB_Set3dCombMid(DISABLE); in HAL_AVD_COMB_SetNonStandardHtotal()
4558 RIU_WriteRegBit(BK_COMB_18, DISABLE, BIT(0)); in HAL_AVD_COMB_SetNonStandardHtotal()
4565 RIU_WriteRegBit(BK_COMB_C0, DISABLE, BIT(5)); in HAL_AVD_COMB_SetNonStandardHtotal()
4657 RIU_WriteRegBit(BK_VBI_8D, DISABLE, BIT(6)); in HAL_AVD_VBI_SetTTSigDetSel()
4728 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_SetPQFineTune()