Lines Matching refs:DISABLE
6374 HAL_AVD_VDMCU_SetFreeze(DISABLE); in HAL_AVD_VDMCU_SetClock()
6438 HAL_AVD_VDMCU_SetFreeze(DISABLE); in HAL_AVD_VDMCU_SetClock()
6517 RIU_WriteRegBit(VD_MCU_SRAM_EN, DISABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6556 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, DISABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6565 HAL_AVD_VDMCU_SetFreeze(DISABLE); in HAL_AVD_VDMCU_LoadDSP()
6608 RIU_WriteRegBit(BK_AFEC_14, DISABLE, BIT(7)); in HAL_AVD_RegInit()
6836 RIU_WriteRegBit(BK_AFEC_16, DISABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
6848 HAL_AVD_VDMCU_SetFreeze(DISABLE); in HAL_AVD_AFEC_McuReset()
6984 RIU_WriteRegBit(L_BK_CLKGEN0(0x00), DISABLE, BIT(4)); in HAL_AVD_AFEC_SetClockSource()
7145 RIU_WriteRegBit (BK_COMB_10, DISABLE, BIT(7)); // <- SET COMB in HAL_AVD_AFEC_SetInput()
7150 RIU_WriteRegBit( BK_AFEC_1F, DISABLE, BIT(7)); // disable clamp C in HAL_AVD_AFEC_SetInput()
7165 RIU_WriteRegBit (BK_COMB_10, DISABLE, BIT(7)); // <- SET COMB in HAL_AVD_AFEC_SetInput()
7170 RIU_WriteRegBit( BK_AFEC_1F, DISABLE, BIT(7)); // disable clamp C in HAL_AVD_AFEC_SetInput()
7179 HAL_AVD_COMB_Set3dCombMid(DISABLE); in HAL_AVD_AFEC_SetInput()
7206 RIU_WriteRegBit (BK_COMB_10, DISABLE, BIT(7)); // <- SET COMB in HAL_AVD_AFEC_SetInput()
7211 RIU_WriteRegBit( BK_AFEC_1F, DISABLE, BIT(7)); // disable clamp C in HAL_AVD_AFEC_SetInput()
7249 RIU_WriteRegBit(BK_AFEC_8F,DISABLE,BIT(5)); in HAL_AVD_AFEC_SetInput()
7264 RIU_WriteRegBit(BK_AFEC_CF,DISABLE,BIT(7)); in HAL_AVD_AFEC_SetInput()
7265 RIU_WriteRegBit(H_BK_CHIPTOP(0x13), DISABLE, BIT(8)); //20090611EL in HAL_AVD_AFEC_SetInput()
7266 …RIU_WriteRegBit(BK_AFEC_40,DISABLE,BIT(4)); // BY 20090630 put gain setting temporarily, TODO move… in HAL_AVD_AFEC_SetInput()
7267 RIU_WriteRegBit(BK_AFEC_40,DISABLE,BIT(7)); // disable VIF in hardware in HAL_AVD_AFEC_SetInput()
7275 HAL_AVD_AFEC_EnableCVBSLPF(DISABLE); in HAL_AVD_AFEC_SetInput()
7276 RIU_WriteRegBit(BK_AFEC_8F,DISABLE,BIT(5)); in HAL_AVD_AFEC_SetInput()
7280 RIU_WriteRegBit(BK_AFEC_CF,DISABLE,BIT(7)); in HAL_AVD_AFEC_SetInput()
7281 RIU_WriteRegBit(H_BK_CHIPTOP(0x13), DISABLE, BIT(8)); //20090611EL in HAL_AVD_AFEC_SetInput()
7282 …RIU_WriteRegBit(BK_AFEC_40,DISABLE,BIT(4)); // BY 20090630 put gain setting temporarily, TODO move… in HAL_AVD_AFEC_SetInput()
7283 RIU_WriteRegBit(BK_AFEC_40,DISABLE,BIT(7)); // disable VIF in hardware in HAL_AVD_AFEC_SetInput()
7388 RIU_WriteRegBit(BK_AFEC_A0, DISABLE, BIT(7)); in HAL_AVD_AFEC_SetHTotal()
7392 RIU_WriteRegBit(BK_COMB_50, DISABLE, BIT(0)); in HAL_AVD_AFEC_SetHTotal()
7487 HAL_AVD_AFEC_Set656DCOffset(DISABLE); in HAL_AVD_AFEC_SetFSCMode()
7493 HAL_AVD_COMB_Set3dCombMid(DISABLE); in HAL_AVD_AFEC_SetFSCMode()
7575 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetMode()
7596 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetCoarseGain()
7617 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetFineGain()
7789 RIU_WriteRegBit(BK_COMB_EE, DISABLE, BIT(7)); in HAL_AVD_COMB_Set3dCombMid()
7790 RIU_WriteRegBit(BK_COMB_2D, DISABLE, BIT(4)); in HAL_AVD_COMB_Set3dCombMid()
7823 … RIU_WriteRegBit( BK_COMB_2D, DISABLE, BIT(4)); // T3 Transition Vertical line in channel change. in HAL_AVD_COMB_Set3dComb()
7825 HAL_AVD_COMB_Set3dCombMid(DISABLE); in HAL_AVD_COMB_Set3dComb()
8048 HAL_AVD_COMB_Set3dCombMid(DISABLE); in HAL_AVD_COMB_SetNonStandardHtotal()
8050 RIU_WriteRegBit(BK_COMB_18, DISABLE, BIT(0)); in HAL_AVD_COMB_SetNonStandardHtotal()
8057 RIU_WriteRegBit(BK_COMB_C0, DISABLE, BIT(5)); in HAL_AVD_COMB_SetNonStandardHtotal()
8142 RIU_WriteRegBit(BK_COMB_4C, DISABLE, BIT(7)); in HAL_AVD_COMB_SetMemoryRequest()
8177 RIU_WriteRegBit(BK_VBI_8D, DISABLE, BIT(6)); in HAL_AVD_VBI_SetTTSigDetSel()
8248 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_SetPQFineTune()