Lines Matching refs:RIU_WriteByte
154 #define RIU_WriteByte( u32Reg, u8Val ) \ macro
6215 …RIU_WriteByte( (((MS_U16)(VdDecTbl[u16Index*3])<<8)+VdDecTbl[u16Index*3+1]), (VdDecTbl[u16Index*3+… in HAL_AVD_WriteRegTbl()
6259 RIU_WriteByte(BK_AFEC_C2, 0xA5); in HAL_AVD_VDMCU_SoftStop()
6260 RIU_WriteByte(BK_AFEC_C0, 0xFA); in HAL_AVD_VDMCU_SoftStop()
6269 RIU_WriteByte(BK_AFEC_C2, 0x00); in HAL_AVD_VDMCU_SoftStop()
6270 RIU_WriteByte(BK_AFEC_C0, 0x00); in HAL_AVD_VDMCU_SoftStop()
6526 RIU_WriteByte(VD_MCU_ADDR_L, 0x00); in HAL_AVD_VDMCU_LoadDSP()
6527 RIU_WriteByte(VD_MCU_ADDR_H, 0x00); in HAL_AVD_VDMCU_LoadDSP()
6534 RIU_WriteByte(VD_MCU_SRAM_WD, pu8VD_DSP[u32I]); in HAL_AVD_VDMCU_LoadDSP()
6539 RIU_WriteByte(VD_MCU_ADDR_L, 0x00); in HAL_AVD_VDMCU_LoadDSP()
6540 RIU_WriteByte(VD_MCU_ADDR_H, 0x00); in HAL_AVD_VDMCU_LoadDSP()
6630 … RIU_WriteByte( astVdDecInitialize[i].u16Index, astVdDecInitialize[i].u8Value ); // write register in HAL_AVD_RegInit()
6693 RIU_WriteByte( BK_AFEC_04, 0x21 ); in HAL_AVD_AFEC_GetHWHsync()
6800 RIU_WriteByte(BK_AFEC_04, 0x04); in HAL_AVD_AFEC_GetNoiseMag()
6996 RIU_WriteByte(H_BK_ADC_ATOP(0x04), 0xB7); in HAL_AVD_AFEC_SetClockSource()
6997 RIU_WriteByte(L_BK_ADC_ATOP(0x04), 0xE0); in HAL_AVD_AFEC_SetClockSource()
6998 RIU_WriteByte(H_BK_ADC_ATOP(0x05), 0x07); in HAL_AVD_AFEC_SetClockSource()
6999 RIU_WriteByte(L_BK_ADC_ATOP(0x05), 0x3D); in HAL_AVD_AFEC_SetClockSource()
7000 RIU_WriteByte(H_BK_ADC_ATOP(0x06), 0xEB); in HAL_AVD_AFEC_SetClockSource()
7001 RIU_WriteByte(L_BK_ADC_ATOP(0x06), 0x7E); in HAL_AVD_AFEC_SetClockSource()
7002 RIU_WriteByte(H_BK_ADC_ATOP(0x5E), 0x1F); // new after T4 in HAL_AVD_AFEC_SetClockSource()
7012 RIU_WriteByte(0x3314L, 0x00); // Enable ADC clock in HAL_AVD_AFEC_SetClockSource()
7013 RIU_WriteByte(0x3315L, 0x01); in HAL_AVD_AFEC_SetClockSource()
7014 RIU_WriteByte(0x330AL, 0x00); // ADC_CLK in HAL_AVD_AFEC_SetClockSource()
7015 RIU_WriteByte(0x330BL, 0x00); in HAL_AVD_AFEC_SetClockSource()
7016 RIU_WriteByte(0x331AL, 0x04); // MPLLDIV10/2=43MHz in HAL_AVD_AFEC_SetClockSource()
7017 RIU_WriteByte(0x331BL, 0x04); // MPLLDIV10/2=43MHz in HAL_AVD_AFEC_SetClockSource()
7018 RIU_WriteByte(0x331CL, 0x00); // MPLLDIV10/2=43MHz in HAL_AVD_AFEC_SetClockSource()
7019 RIU_WriteByte(0x331DL, 0x00); // ADC_CLKOUT=144MHz in HAL_AVD_AFEC_SetClockSource()
7022 RIU_WriteByte(0x12002L, 0x04); // Enable VIF in HAL_AVD_AFEC_SetClockSource()
7023 RIU_WriteByte(0x12003L, 0x00); in HAL_AVD_AFEC_SetClockSource()
7026 RIU_WriteByte(0x1286AL, 0x04); // Reset MPLL in HAL_AVD_AFEC_SetClockSource()
7027 RIU_WriteByte(0x1286BL, 0x1E); in HAL_AVD_AFEC_SetClockSource()
7028 RIU_WriteByte(0x1286AL, 0x04); // Disable MPLL reset in HAL_AVD_AFEC_SetClockSource()
7029 RIU_WriteByte(0x1286BL, 0x06); in HAL_AVD_AFEC_SetClockSource()
7030 RIU_WriteByte(0x12869L, 0x00); // BY 20090715, ATSC will overwrite this value in HAL_AVD_AFEC_SetClockSource()
7031 RIU_WriteByte(0x12866L, 0x02); // Set MPLL_LOOP_DIV_FIRST and SECOND in HAL_AVD_AFEC_SetClockSource()
7032 RIU_WriteByte(0x12867L, 0x09); in HAL_AVD_AFEC_SetClockSource()
7033 RIU_WriteByte(0x12860L, 0x00); // Set MPLL_ADC_DIV_SEL in HAL_AVD_AFEC_SetClockSource()
7034 RIU_WriteByte(0x12861L, 0x06); in HAL_AVD_AFEC_SetClockSource()
7035 RIU_WriteByte(0x12802L, 0x1C); // Set IMUXS QMUXS in HAL_AVD_AFEC_SetClockSource()
7036 RIU_WriteByte(0x12803L, 0x11); in HAL_AVD_AFEC_SetClockSource()
7037 RIU_WriteByte(0x12818L, 0x00); // Set enable ADC clock in HAL_AVD_AFEC_SetClockSource()
7038 RIU_WriteByte(0x12819L, 0x00); in HAL_AVD_AFEC_SetClockSource()
7039 RIU_WriteByte(0x12840L, 0x60); // Disable PWDN_REF in HAL_AVD_AFEC_SetClockSource()
7040 RIU_WriteByte(0x12841L, 0x00); in HAL_AVD_AFEC_SetClockSource()
7041 RIU_WriteByte(0x12816L, 0x05); in HAL_AVD_AFEC_SetClockSource()
7042 RIU_WriteByte(0x12817L, 0x05); in HAL_AVD_AFEC_SetClockSource()
7045 RIU_WriteByte(0x12802L, 0x0C); in HAL_AVD_AFEC_SetClockSource()
7046 RIU_WriteByte(0x12803L, 0x10); in HAL_AVD_AFEC_SetClockSource()
7115 RIU_WriteByte (L_BK_ADC_ATOP(0x40), in HAL_AVD_AFEC_SetInput()
7118 RIU_WriteByte (L_BK_ADC_ATOP(0x42), 0xEC); // i.e. 0x83 in HAL_AVD_AFEC_SetInput()
7123 RIU_WriteByte (L_BK_ADC_ATOP(0x40), in HAL_AVD_AFEC_SetInput()
7126 RIU_WriteByte (L_BK_ADC_ATOP(0x42), 0xEC); // i.e. 0x83 in HAL_AVD_AFEC_SetInput()
7132 RIU_WriteByte (L_BK_ADC_ATOP(0x42), 0xEC); // i.e. 0x83 in HAL_AVD_AFEC_SetInput()
7149 RIU_WriteByte( BK_AFEC_1A, ( RIU_ReadByte( BK_AFEC_1A ) ) & ~0xC0 ); // disable SV input in HAL_AVD_AFEC_SetInput()
7152 RIU_WriteByte( BK_AFEC_7F, 0x65); // Switch to Comb Y/U/V 444 input. in HAL_AVD_AFEC_SetInput()
7169 RIU_WriteByte( BK_AFEC_1A, ( RIU_ReadByte( BK_AFEC_1A ) ) & ~0xC0 ); // disable SV input in HAL_AVD_AFEC_SetInput()
7172 RIU_WriteByte( BK_AFEC_7F, 0x65); // Switch to Comb Y/U/V 444 input. in HAL_AVD_AFEC_SetInput()
7191 RIU_WriteByte( BK_AFEC_1A, ( RIU_ReadByte(BK_AFEC_1A) )| 0xC0); // Enable SV input in HAL_AVD_AFEC_SetInput()
7194 … RIU_WriteByte( BK_AFEC_7F, 0x65); // Switch to Comb Y/U/V 444 input. <- 0x65 used in Saturn in HAL_AVD_AFEC_SetInput()
7210 RIU_WriteByte( BK_AFEC_1A, ( RIU_ReadByte( BK_AFEC_1A ) ) & ~0xC0 ); // disable SV input in HAL_AVD_AFEC_SetInput()
7213 RIU_WriteByte (H_BK_ADC_ATOP(0x44), 0xFF); // i.e. ATOP 0x88 in HAL_AVD_AFEC_SetInput()
7214 RIU_WriteByte (L_BK_ADC_ATOP(0x44), 0x10); // i.e. ATOP 0x87 in HAL_AVD_AFEC_SetInput()
7215 RIU_WriteByte (L_BK_ADC_ATOP(0x41), 0x18); // i.e. ATOP 0x81 in HAL_AVD_AFEC_SetInput()
7216 RIU_WriteByte (H_BK_ADC_ATOP(0x41), 0x40); // i.e. ATOP 0x82 in HAL_AVD_AFEC_SetInput()
7217 RIU_WriteByte (H_BK_ADC_ATOP(0x43), 0x2E); // i.e. ATOP 0x85 in HAL_AVD_AFEC_SetInput()
7218 RIU_WriteByte (L_BK_ADC_ATOP(0x43), 0x30); // i.e. ATOP 0x84 in HAL_AVD_AFEC_SetInput()
7220 RIU_WriteByte (L_BK_ADC_ATOP(0x1C), RIU_ReadByte(L_BK_ADC_ATOP(0x1C)) & 0xE0); in HAL_AVD_AFEC_SetInput()
7221 …RIU_WriteByte (L_BK_ADC_ATOP(0x2C), 0x00); // i.e. ATOP 0x58 set VClamp to VCLAMP_RGB_ClampGnd (i.… in HAL_AVD_AFEC_SetInput()
7222 RIU_WriteByte (H_BK_ADC_ATOP(0x1C), 0x40); // i.e. ATOP 0x37 in HAL_AVD_AFEC_SetInput()
7223 RIU_WriteByte (L_BK_ADC_ATOP(0x4C), 0xA1); // i.e. ATOP 0x98 in HAL_AVD_AFEC_SetInput()
7227 RIU_WriteByte (L_BK_ADC_DTOP(0x0B), 0xFF); // i.e. DTOP 0x14 set clamp placement in HAL_AVD_AFEC_SetInput()
7228 RIU_WriteByte (H_BK_ADC_DTOP(0x0B), 0x40); // i.e. DTOP 0x15 set clamp duration in HAL_AVD_AFEC_SetInput()
7229 RIU_WriteByte (L_BK_ADC_DTOP(0x07), 0x8A); // i.e. DTOP 0x0D in HAL_AVD_AFEC_SetInput()
7230 RIU_WriteByte (L_BK_ADC_DTOP(0x10), 0x00); // i.e. DTOP 0x20 in HAL_AVD_AFEC_SetInput()
7232 RIU_WriteByte(BK_AFEC_7F, 0x66); // Switch to Comb Y/U/V 444 input. in HAL_AVD_AFEC_SetInput()
7258 RIU_WriteByte(BK_AFEC_8F,0x3D); in HAL_AVD_AFEC_SetInput()
7259 RIU_WriteByte(BK_AFEC_20,0xBC); in HAL_AVD_AFEC_SetInput()
7260 RIU_WriteByte(BK_AFEC_21,0x1D); in HAL_AVD_AFEC_SetInput()
7268 RIU_WriteByte(BK_AFEC_8F,0x19); in HAL_AVD_AFEC_SetInput()
7269 RIU_WriteByte(BK_AFEC_20,0xB0); in HAL_AVD_AFEC_SetInput()
7270 RIU_WriteByte(BK_AFEC_21,0x19); in HAL_AVD_AFEC_SetInput()
7284 RIU_WriteByte(BK_AFEC_8F,0x19); in HAL_AVD_AFEC_SetInput()
7285 RIU_WriteByte(BK_AFEC_20,0xB0); in HAL_AVD_AFEC_SetInput()
7286 RIU_WriteByte(BK_AFEC_21,0x19); in HAL_AVD_AFEC_SetInput()
7367 RIU_WriteByte(BK_AFEC_A1, 0x6A); in HAL_AVD_AFEC_SetHTotal()
7368 RIU_WriteByte(BK_AFEC_A0, 0x3C); in HAL_AVD_AFEC_SetHTotal()
7378 RIU_WriteByte(BK_AFEC_9D, u32Mid >> 3); in HAL_AVD_AFEC_SetHTotal()
7379 RIU_WriteByte(BK_AFEC_9E, (MS_U8)(u32Mid &0x07) << 5); in HAL_AVD_AFEC_SetHTotal()
7382 RIU_WriteByte(BK_AFEC_9D, u32HTotal >> 3); in HAL_AVD_AFEC_SetHTotal()
7383 RIU_WriteByte(BK_AFEC_9E, (MS_U8)(u32HTotal & 0x07) << 5); in HAL_AVD_AFEC_SetHTotal()
7385 RIU_WriteByte(BK_AFEC_A1, u8A1Backup); in HAL_AVD_AFEC_SetHTotal()
7386 RIU_WriteByte(BK_AFEC_A0, u8A0Backup); in HAL_AVD_AFEC_SetHTotal()
7444 RIU_WriteByte(BK_AFEC_7B, u8BT656Width); // 656_HDES in HAL_AVD_AFEC_SetBT656Width()
7613 RIU_WriteByte (BK_AFEC_44, u8AgcFineGain); in HAL_AVD_AFEC_AGCSetFineGain()
7637 RIU_WriteByte (BK_AFEC_D7, u8ColorKillLevel); in HAL_AVD_AFEC_SetColorKillLevel()
7654 RIU_WriteByte (BK_AFEC_99, (eVDHsyncSensitivityTuning.u8DetectWinAfterLock & 0x0F) << 4 in HAL_AVD_AFEC_SetHsyncSensitivity()
7709 RIU_WriteByte(BK_AFEC_E3, u8Value); // decrease color stripe threshold for non-standard signals in HAL_AVD_AFEC_SetColorStripe()
7726 RIU_WriteByte(BK_COMB_E0,0xff); in HAL_AVD_COMB_Get3dCombTimingCheck()
7755 …RIU_WriteByte(BK_COMB_3F,(u32COMB_3D_Addr>> 4) & 0xFF); // <-<<< set 3D COMB BUF S… in HAL_AVD_COMB_SetMemoryProtect()
7756 …RIU_WriteByte(BK_COMB_3E,(u32COMB_3D_Addr >> 12) & 0xFF); // <-<<< set 3D COMB BUF S… in HAL_AVD_COMB_SetMemoryProtect()
7757 …RIU_WriteByte(BK_COMB_3D,(u32COMB_3D_Addr >> 20) & 0xFF); // <-<<< set 3D COMB BUF S… in HAL_AVD_COMB_SetMemoryProtect()
7758 …RIU_WriteByte(BK_COMB_67,(u32COMB_3D_Addr >> 28) & 0x07); // 20141104 Dia Add Comb_6… in HAL_AVD_COMB_SetMemoryProtect()
7760 …RIU_WriteByte(BK_COMB_68,(u32COMB_3D_Addr+u32COMB_3D_Len) >> 28); // 20110721 Brian Add Com… in HAL_AVD_COMB_SetMemoryProtect()
7761 …RIU_WriteByte(BK_COMB_88,(u32COMB_3D_Addr+u32COMB_3D_Len) >> 20); // COMB memory protect add… in HAL_AVD_COMB_SetMemoryProtect()
7762 …RIU_WriteByte(BK_COMB_89,(u32COMB_3D_Addr+u32COMB_3D_Len) >> 12); // COMB memory protect add… in HAL_AVD_COMB_SetMemoryProtect()
7763 …RIU_WriteByte(BK_COMB_8A,(u32COMB_3D_Addr+u32COMB_3D_Len) >> 4); // COMB memory protect add… in HAL_AVD_COMB_SetMemoryProtect()
7852 RIU_WriteByte( BK_COMB_57, u8COMB57 ); in HAL_AVD_COMB_Set3dCombSpeed()
7853 RIU_WriteByte( BK_COMB_58, u8COMB58 ); in HAL_AVD_COMB_Set3dCombSpeed()
7871 RIU_WriteByte(BK_COMB_55, u8Threshold); in HAL_AVD_COMB_Set3dDetectionTolerance()
7891 RIU_WriteByte(BK_COMB_9F, 0xc8); in HAL_AVD_COMB_Set3dFineTune()
7892 RIU_WriteByte(BK_COMB_ED, 0x82); in HAL_AVD_COMB_Set3dFineTune()
7897 RIU_WriteByte(BK_COMB_9F, 0xc6); in HAL_AVD_COMB_Set3dFineTune()
7898 RIU_WriteByte(BK_COMB_ED, 0x80); in HAL_AVD_COMB_Set3dFineTune()
7916 RIU_WriteByte( BK_COMB_F2, u8Value ); in HAL_AVD_COMB_SetF2()
7944 RIU_WriteByte(BK_COMB_C0,0x60); in HAL_AVD_COMB_SetNonStandardFSC()
7957 RIU_WriteByte(BK_COMB_C0,0xA0); in HAL_AVD_COMB_SetNonStandardFSC()
8106 RIU_WriteByte( BK_COMB_5A, u8Tolerance); in HAL_AVD_COMB_SetHsyncTolerance()
8130 …RIU_WriteByte(BK_COMB_68,(g_u32COMB_3D_Addr+g_u32COMB_3D_Len) >> 28); // 20110721 Brian Add… in HAL_AVD_COMB_SetMemoryRequest()
8131 …RIU_WriteByte(BK_COMB_88,(g_u32COMB_3D_Addr+g_u32COMB_3D_Len) >> 20); // COMB memory protect… in HAL_AVD_COMB_SetMemoryRequest()
8132 …RIU_WriteByte(BK_COMB_89,(g_u32COMB_3D_Addr+g_u32COMB_3D_Len) >> 12); // COMB memory protect… in HAL_AVD_COMB_SetMemoryRequest()
8133 …RIU_WriteByte(BK_COMB_8A,(g_u32COMB_3D_Addr+g_u32COMB_3D_Len) >> 4); // COMB memory protect… in HAL_AVD_COMB_SetMemoryRequest()
8142 …RIU_WriteByte(BK_COMB_68,(g_u32COMB_3D_Addr) >> 28); // 20110721 Brian Add Comb_68[2:0] Enh… in HAL_AVD_COMB_SetMemoryRequest()
8143 … RIU_WriteByte(BK_COMB_88,(g_u32COMB_3D_Addr) >> 20); // COMB memory protect address - H in HAL_AVD_COMB_SetMemoryRequest()
8144 … RIU_WriteByte(BK_COMB_89,(g_u32COMB_3D_Addr) >> 12); // COMB memory protect address - M in HAL_AVD_COMB_SetMemoryRequest()
8145 … RIU_WriteByte(BK_COMB_8A,(g_u32COMB_3D_Addr) >> 4); // COMB memory protect address - L in HAL_AVD_COMB_SetMemoryRequest()
8228 RIU_WriteByte( u16Addr ,u8Value); in HAL_AVD_SetReg()
8275 RIU_WriteByte(BK_AFEC_4F, 0x76); in HAL_AVD_AFEC_BackPorchWindowPosition()
8280 RIU_WriteByte(BK_AFEC_4F, 0x50); in HAL_AVD_AFEC_BackPorchWindowPosition()
8285 RIU_WriteByte(BK_AFEC_4F, u8Value); in HAL_AVD_AFEC_BackPorchWindowPosition()
8333 RIU_WriteByte(BK_AFEC_80, 0x17); in HAL_AVD_ShiftClk()
8334 RIU_WriteByte(BK_AFEC_81, 0x77); in HAL_AVD_ShiftClk()
8335 RIU_WriteByte(BK_AFEC_82, 0x78); in HAL_AVD_ShiftClk()
8336 RIU_WriteByte(BK_AFEC_8F, 0x0D); in HAL_AVD_ShiftClk()
8339 RIU_WriteByte(BK_AFEC_80, 0x12); in HAL_AVD_ShiftClk()
8340 RIU_WriteByte(BK_AFEC_81, 0xF2); in HAL_AVD_ShiftClk()
8341 RIU_WriteByte(BK_AFEC_82, 0x37); in HAL_AVD_ShiftClk()
8342 RIU_WriteByte(BK_AFEC_8F, 0x0D); in HAL_AVD_ShiftClk()
8345 RIU_WriteByte(BK_AFEC_80, 0x17); in HAL_AVD_ShiftClk()
8346 RIU_WriteByte(BK_AFEC_81, 0x7E); in HAL_AVD_ShiftClk()
8347 RIU_WriteByte(BK_AFEC_82, 0x13); in HAL_AVD_ShiftClk()
8348 RIU_WriteByte(BK_AFEC_8F, 0x0D); in HAL_AVD_ShiftClk()
8351 RIU_WriteByte(BK_AFEC_80, 0x17); in HAL_AVD_ShiftClk()
8352 RIU_WriteByte(BK_AFEC_81, 0x73); in HAL_AVD_ShiftClk()
8353 RIU_WriteByte(BK_AFEC_82, 0x41); in HAL_AVD_ShiftClk()
8354 RIU_WriteByte(BK_AFEC_8F, 0x0D); in HAL_AVD_ShiftClk()
8357 RIU_WriteByte(BK_AFEC_80, 0x13); in HAL_AVD_ShiftClk()
8358 RIU_WriteByte(BK_AFEC_81, 0x9A); in HAL_AVD_ShiftClk()
8359 RIU_WriteByte(BK_AFEC_82, 0x41); in HAL_AVD_ShiftClk()
8360 RIU_WriteByte(BK_AFEC_8F, 0x0D); in HAL_AVD_ShiftClk()
8363 RIU_WriteByte(BK_AFEC_80, 0x12); in HAL_AVD_ShiftClk()
8364 RIU_WriteByte(BK_AFEC_81, 0xF2); in HAL_AVD_ShiftClk()
8365 RIU_WriteByte(BK_AFEC_82, 0x37); in HAL_AVD_ShiftClk()
8366 RIU_WriteByte(BK_AFEC_8F, 0x0D); in HAL_AVD_ShiftClk()
8375 RIU_WriteByte(BK_AFEC_80, 0x18); in HAL_AVD_ShiftClk()
8376 RIU_WriteByte(BK_AFEC_81, 0xCE); in HAL_AVD_ShiftClk()
8377 RIU_WriteByte(BK_AFEC_82, 0xC0); in HAL_AVD_ShiftClk()
8378 RIU_WriteByte(BK_AFEC_8F, 0x0D); in HAL_AVD_ShiftClk()
8381 RIU_WriteByte(BK_AFEC_80, 0x14); in HAL_AVD_ShiftClk()
8382 RIU_WriteByte(BK_AFEC_81, 0x07); in HAL_AVD_ShiftClk()
8383 RIU_WriteByte(BK_AFEC_82, 0x5F); in HAL_AVD_ShiftClk()
8384 RIU_WriteByte(BK_AFEC_8F, 0x0D); in HAL_AVD_ShiftClk()
8387 RIU_WriteByte(BK_AFEC_80, 0x18); in HAL_AVD_ShiftClk()
8388 RIU_WriteByte(BK_AFEC_81, 0xD5); in HAL_AVD_ShiftClk()
8389 RIU_WriteByte(BK_AFEC_82, 0xBD); in HAL_AVD_ShiftClk()
8390 RIU_WriteByte(BK_AFEC_8F, 0x0D); in HAL_AVD_ShiftClk()
8393 RIU_WriteByte(BK_AFEC_80, 0x18); in HAL_AVD_ShiftClk()
8394 RIU_WriteByte(BK_AFEC_81, 0xCA); in HAL_AVD_ShiftClk()
8395 RIU_WriteByte(BK_AFEC_82, 0x4D); in HAL_AVD_ShiftClk()
8396 RIU_WriteByte(BK_AFEC_8F, 0x0D); in HAL_AVD_ShiftClk()
8399 RIU_WriteByte(BK_AFEC_80, 0x14); in HAL_AVD_ShiftClk()
8400 RIU_WriteByte(BK_AFEC_81, 0xB9); in HAL_AVD_ShiftClk()
8401 RIU_WriteByte(BK_AFEC_82, 0x03); in HAL_AVD_ShiftClk()
8402 RIU_WriteByte(BK_AFEC_8F, 0x0D); in HAL_AVD_ShiftClk()
8405 RIU_WriteByte(BK_AFEC_80, 0x14); in HAL_AVD_ShiftClk()
8406 RIU_WriteByte(BK_AFEC_81, 0x07); in HAL_AVD_ShiftClk()
8407 RIU_WriteByte(BK_AFEC_82, 0x5F); in HAL_AVD_ShiftClk()
8408 RIU_WriteByte(BK_AFEC_8F, 0x0D); in HAL_AVD_ShiftClk()
8416 RIU_WriteByte(BK_AFEC_8F, 0x3D); in HAL_AVD_ShiftClk()
8420 RIU_WriteByte(BK_AFEC_8F, 0x1D); //AFEC_8F[4]=1, use HW mode default is 43.2Mz in HAL_AVD_ShiftClk()