484 void xhci_ppc(struct xhc_comp *xhci, int bOn)  in xhci_ppc()  argument
491    switch (xhci->port_index) {  in xhci_ppc()
493        addr_w = usb_readw((void*)(xhci->u3top_base+0xFC*2));  in xhci_ppc()
495        addr_w = usb_readw((void*)(xhci->u3top_base+0xFE*2));  in xhci_ppc()
501        addr_w = usb_readw((void*)(xhci->u3top_base+0xE6*2));  in xhci_ppc()
503        addr_w = usb_readw((void*)(xhci->u3top_base+0xE8*2));  in xhci_ppc()
514 …  diag_printf("xhci_ppc: turn %s USB3.0 port %d power \n", (bOn) ? "on" : "off", xhci->port_index);  in xhci_ppc()
538 void U3phy_MS28_init(struct xhc_comp *xhci)  in U3phy_MS28_init()  argument
541 …writeb(readb((void*)(xhci->u3phy_D_base+0x84*2))|0x40, (void*)(xhci->u3phy_D_base+0x84*2)); // ope…  in U3phy_MS28_init()
545 …writew(0x0104, (void*) (xhci->u3phy_A_base+0x6*2));  // for Enable 1G clock pass to UTMI //[2] reg…  in U3phy_MS28_init()
548 	writew(0x0,    (void*) (xhci->u3phy_A_base)); 		 // power on rx atop  in U3phy_MS28_init()
549 	writew(0x0,    (void*) (xhci->u3phy_A_base+0x2*2));	 // power on tx atop  in U3phy_MS28_init()
551 	writew(0x0,    (void*) (xhci->u3phy_A_base+0x3A*2));  // overwrite power on rx/tx atop  in U3phy_MS28_init()
552 	writew(0x0160, (void*) (xhci->u3phy_D_base+0x18*2));  in U3phy_MS28_init()
553 	writew(0x0,    (void*) (xhci->u3phy_D_base+0x20*2));	 // power on u3_phy clockgen  in U3phy_MS28_init()
554 	writew(0x0,    (void*) (xhci->u3phy_D_base+0x22*2));	 // power on u3_phy clockgen  in U3phy_MS28_init()
557 …writew(0x308,    (void*) (xhci->u3phy_A_base+0x3A*2)); // [9,8,3] PD_TXCLK_USB3TXPLL, PD_USB3_IBIA…  in U3phy_MS28_init()
558 …writeb(readb((void*)(xhci->u3phy_A_base+0x3*2-1)) & 0xbb,     (void*)(xhci->u3phy_A_base+0x3*2-1))…  in U3phy_MS28_init()
560 	writeb(0xF4,   (void*) (xhci->u3phy_D_base+0x12*2));	  //TX lock threshold  in U3phy_MS28_init()
594 void xhci_ssport_set_state(struct xhc_comp *xhci, int bOn)  in xhci_ssport_set_state()  argument
598     temp = readl((void*)(xhci->xhci_port_addr));  in xhci_ssport_set_state()
599     diag_printf("port status 0x%lx: 0x%lx\n", xhci->xhci_port_addr, temp);  in xhci_ssport_set_state()
607             writel(temp, (void*)(xhci->xhci_port_addr));  in xhci_ssport_set_state()
610             temp = readl((void*)(xhci->xhci_port_addr));  in xhci_ssport_set_state()
617             writel(temp | PORT_PE, (void*)(xhci->xhci_port_addr));  in xhci_ssport_set_state()
620             temp = readl((void*)(xhci->xhci_port_addr));  in xhci_ssport_set_state()