Lines Matching refs:writew
360 writew(t_off2, (void*)(BDMA_RIU_BASE+0x4*2));
362 writew(s & 0xffff, (void*)(BDMA_RIU_BASE+0x8*2));
363 writew((s>>16) & 0xffff, (void*)(BDMA_RIU_BASE+0xA*2));
365 writew(t & 0xffff, (void*)(BDMA_RIU_BASE+0xC*2));
366 writew((t>>16) & 0xffff, (void*)(BDMA_RIU_BASE+0xE*2));
368 writew(0x4, (void*)(BDMA_RIU_BASE+0x10*2));
374 writew(readw((void*)(BDMA_RIU_BASE)) | 0x1, (void*)(BDMA_RIU_BASE));
545 …writew(0x0104, (void*) (xhci->u3phy_A_base+0x6*2)); // for Enable 1G clock pass to UTMI //[2] reg… in U3phy_MS28_init()
548 writew(0x0, (void*) (xhci->u3phy_A_base)); // power on rx atop in U3phy_MS28_init()
549 writew(0x0, (void*) (xhci->u3phy_A_base+0x2*2)); // power on tx atop in U3phy_MS28_init()
551 writew(0x0, (void*) (xhci->u3phy_A_base+0x3A*2)); // overwrite power on rx/tx atop in U3phy_MS28_init()
552 writew(0x0160, (void*) (xhci->u3phy_D_base+0x18*2)); in U3phy_MS28_init()
553 writew(0x0, (void*) (xhci->u3phy_D_base+0x20*2)); // power on u3_phy clockgen in U3phy_MS28_init()
554 writew(0x0, (void*) (xhci->u3phy_D_base+0x22*2)); // power on u3_phy clockgen in U3phy_MS28_init()
557 …writew(0x308, (void*) (xhci->u3phy_A_base+0x3A*2)); // [9,8,3] PD_TXCLK_USB3TXPLL, PD_USB3_IBIA… in U3phy_MS28_init()