Lines Matching refs:SEAL_SECURE1_RANGE0
118 #define SEAL_SECURE1_RANGE0 (0x23800) macro
156 #define REG_SECURE1_RANGE0_START_ADDR (SEAL_SECURE1_RANGE0+0x00)
157 #define REG_SECURE1_RANGE0_END_ADDR (SEAL_SECURE1_RANGE0+0x08)
158 #define REG_SECURE1_RANGE0_ATTRIBUTE (SEAL_SECURE1_RANGE0+0x0E)
160 #define REG_SECURE1_RANGE1_START_ADDR (SEAL_SECURE1_RANGE0+0x10)
161 #define REG_SECURE1_RANGE1_END_ADDR (SEAL_SECURE1_RANGE0+0x18)
162 #define REG_SECURE1_RANGE1_ATTRIBUTE (SEAL_SECURE1_RANGE0+0x1E)
164 #define REG_SECURE1_RANGE2_START_ADDR (SEAL_SECURE1_RANGE0+0x20)
165 #define REG_SECURE1_RANGE2_END_ADDR (SEAL_SECURE1_RANGE0+0x28)
166 #define REG_SECURE1_RANGE2_ATTRIBUTE (SEAL_SECURE1_RANGE0+0x2E)
168 #define REG_SECURE1_RANGE3_START_ADDR (SEAL_SECURE1_RANGE0+0x30)
169 #define REG_SECURE1_RANGE3_END_ADDR (SEAL_SECURE1_RANGE0+0x38)
170 #define REG_SECURE1_RANGE3_ATTRIBUTE (SEAL_SECURE1_RANGE0+0x3E)
172 #define REG_SECURE1_RANGE4_START_ADDR (SEAL_SECURE1_RANGE0+0x40)
173 #define REG_SECURE1_RANGE4_END_ADDR (SEAL_SECURE1_RANGE0+0x48)
174 #define REG_SECURE1_RANGE4_ATTRIBUTE (SEAL_SECURE1_RANGE0+0x4E)
176 #define REG_SECURE1_RANGE5_START_ADDR (SEAL_SECURE1_RANGE0+0x50)
177 #define REG_SECURE1_RANGE5_END_ADDR (SEAL_SECURE1_RANGE0+0x58)
178 #define REG_SECURE1_RANGE5_ATTRIBUTE (SEAL_SECURE1_RANGE0+0x5E)
180 #define REG_SECURE1_RANGE6_START_ADDR (SEAL_SECURE1_RANGE0+0x60)
181 #define REG_SECURE1_RANGE6_END_ADDR (SEAL_SECURE1_RANGE0+0x68)
182 #define REG_SECURE1_RANGE6_ATTRIBUTE (SEAL_SECURE1_RANGE0+0x6E)
184 #define REG_SECURE1_RANGE7_START_ADDR (SEAL_SECURE1_RANGE0+0x70)
185 #define REG_SECURE1_RANGE7_END_ADDR (SEAL_SECURE1_RANGE0+0x78)
186 #define REG_SECURE1_RANGE7_ATTRIBUTE (SEAL_SECURE1_RANGE0+0x7E)
190 #define REG_SECURE1_HITTED_STATUS (SEAL_SECURE1_RANGE0+0xE0)
192 #define REG_SECURE1_HITTED_ADDR (SEAL_SECURE1_RANGE0+0xE2)
194 #define REG_SECURE1_HITTED_AUXI_STATUS (SEAL_SECURE1_RANGE0+0xEC)
207 #define REG_SECURE1_LOCK (SEAL_SECURE1_RANGE0+0xFE)