247 #define HAL_ReadRegBit( u32Reg, u8Mask )                                               \  macro
464     if (VOP_MIRROR_CFG_ENABLE != HAL_ReadRegBit(VOP_MIRROR_CFG, VOP_MIRROR_CFG_ENABLE))  in HAL_MVOP_SetVerticalMirrorMode()
482     if (VOP_MIRROR_CFG_ENABLE != HAL_ReadRegBit(VOP_MIRROR_CFG, VOP_MIRROR_CFG_ENABLE))  in HAL_MVOP_SetHorizontallMirrorMode()
615     return (HAL_ReadRegBit(VOP_CTRL0, BIT0));  in HAL_MVOP_GetEnableState()
1712     pMvopTimingInfo->bInterlace = (HAL_ReadRegBit(VOP_CTRL0, BIT7) == BIT7);  in HAL_MVOP_GetTimingInfoFromRegisters()
1998 … if (VOP_LR_DIFF_SIZE == (VOP_LR_DIFF_SIZE & HAL_ReadRegBit(VOP_MULTI_WIN_CFG0, VOP_LR_DIFF_SIZE)))  in HAL_MVOP_Get3DLR2ndCfg()
2059     return (HAL_ReadRegBit(VOP_CTRL0, BIT3) == BIT3);  in HAL_MVOP_GetVerDup()
2078     return ((HAL_ReadRegBit(VOP_RGB_FMT, BIT3) & HAL_ReadRegBit(VOP_CTRL0, BIT3)) == BIT3);  in HAL_MVOP_GetVerx4Dup()
2083     return ((HAL_ReadRegBit(VOP_RGB_FMT, BIT2) & HAL_ReadRegBit(VOP_CTRL0, BIT2)) == BIT2);  in HAL_MVOP_GetHorx4Dup()
2583     if(HAL_ReadRegBit(u32RegMiu, u16Mask))  in HAL_MVOP_GetIsMiuIPControl()
3092     if (VOP_MIRROR_CFG_ENABLE != HAL_ReadRegBit(SUB_REG(VOP_MIRROR_CFG), VOP_MIRROR_CFG_ENABLE))  in HAL_MVOP_SubSetVerticalMirrorMode()
3109     if (VOP_MIRROR_CFG_ENABLE != HAL_ReadRegBit(SUB_REG(VOP_MIRROR_CFG), VOP_MIRROR_CFG_ENABLE))  in HAL_MVOP_SubSetHorizontallMirrorMode()
3205     return (HAL_ReadRegBit(SUB_REG(VOP_CTRL0), BIT0));  in HAL_MVOP_SubGetEnableState()
4097     pMvopTimingInfo->bInterlace = (HAL_ReadRegBit(SUB_REG(VOP_CTRL0), BIT7) == BIT7);  in HAL_MVOP_SubGetTimingInfoFromRegisters()
4139         if (HAL_ReadRegBit(SUB_REG(VOP_MIU_IF), VOP_MIU_128B_I64) != VOP_MIU_128B_I64) //128-bit  in HAL_MVOP_SubSetYUVBaseAdd()