Lines Matching refs:BIT0
146 #define VOP_FLIP_UV BIT0
160 #define VOP_DMA_THD (BIT0|BIT1|BIT2|BIT3|BIT4)
169 #define VOP_BURST_EXT (BIT0|BIT1|BIT2)
200 #define VOP_YUV_STR_HIBITS (BIT4 | BIT3 | BIT2 |BIT1 | BIT0) //Bits(28:24)
205 #define VOP_LOAD_REG BIT0 //load new value into active registers 0x20-0x26
211 #define VOP_MVD_EN BIT0 //t8 new
241 #define VOP_UF BIT0 //buf underflow
245 #define VOP_BIST_FAIL BIT0 //YUV fifo bist fail
264 #define VOP_MSB_MIU_DIFF BIT0
278 #define VOP_INFO_FROM_CODEC_BASE_ADDR (BIT0) //base address
288 #define VOP_INFO_FROM_CODEC_DUAL_BUFF (BIT0) //dual buffer flag
297 #define VOP_EVD_INT_SEP (BIT0)
302 #define VOP_NOT_WAIT_RDLAT (BIT0|BIT1|BIT2)
309 #define VOP_MIRROR_CFG_VEN (BIT0) //vertical mirror enable
317 #define VOP_DC2MVD_FLD_SEL (BIT0) //from maxim, able to control field timing.
322 #define VOP_LR_BUF_MODE (BIT0) //3D L/R dual buffer mode
330 #define VOP_RGB_FMT_565 (BIT0) //RGB 565
332 #define VOP_RGB_FMT_SEL (BIT0 | BIT1) //RGB format selection
339 #define VOP_HS_MODE (BIT0)
353 #define VOP_LSB_REQ_MASK (BIT0 | BIT1) //RGB format selection
371 #define VOP_MFDEC_EN BIT0
380 #define XC_RESET_HCOUNT BIT0
383 #define VOP_420_BW_SAVE_EX BIT0
400 #define CKG_DC0_GATED BIT0
410 #define CKG_SUB_DC0_GATED BIT0
420 #define CKG_DC0_SRAM BIT0
436 #define UPDATE_DC0_FREERUN_CW BIT0
445 #define UPDATE_DC1_FREERUN_CW BIT0
464 #define CKG_FBDEC_GATED BIT0
468 #define REG_MFDEC_CFG BIT0