Lines Matching refs:HAL_MIU_WriteRegBit
141 #define _MaskMiuReq_OPM_R( m ) HAL_MIU_WriteRegBit(MIU_RQ1H_MASK, m, BIT1)
143 #define _MaskMiuReq_DNRB_W( m ) HAL_MIU_WriteRegBit(MIU_RQ1H_MASK, m, BIT2)
144 #define _MaskMiuReq_DNRB_R( m ) HAL_MIU_WriteRegBit(MIU_RQ1H_MASK, m, BIT3)
145 #define _MaskMiuReq_DNRB_RW( m ) HAL_MIU_WriteRegBit(MIU_RQ1H_MASK, m, BIT2|BIT3)
147 #define _MaskMiuReq_SC_RW( m ) HAL_MIU_WriteRegBit(MIU_RQ1H_MASK, m, BIT1|BIT2|BIT3)
149 #define _MaskMiuReq_MVOP_R( m ) HAL_MIU_WriteRegBit(MIU_RQ1L_MASK, m, BIT3)
151 #define _MaskMiuReq_MVD_R( m ) do { HAL_MIU_WriteRegBit(MIU_RQ3L_MASK, m, BIT4); HAL_MIU_WriteR…
152 #define _MaskMiuReq_MVD_W( m ) do { HAL_MIU_WriteRegBit(MIU_RQ3L_MASK, m, BIT4); HAL_MIU_WriteR…
159 #define _MaskMiu1Req_OPM_R( m ) HAL_MIU_WriteRegBit(MIU_RQ1H_MASK, m, BIT1)
161 #define _MaskMiu1Req_DNRB_W( m ) HAL_MIU_WriteRegBit(MIU_RQ1H_MASK, m, BIT2)
162 #define _MaskMiu1Req_DNRB_R( m ) HAL_MIU_WriteRegBit(MIU_RQ1H_MASK, m, BIT3)
163 #define _MaskMiu1Req_DNRB_RW( m ) HAL_MIU_WriteRegBit(MIU_RQ1H_MASK, m, BIT2|BIT3)
165 #define _MaskMiu1Req_SC_RW( m ) HAL_MIU_WriteRegBit(MIU_RQ1H_MASK, m, BIT1|BIT2|BIT3)
167 #define _MaskMiu1Req_MVOP_R( m ) HAL_MIU_WriteRegBit(MIU_RQ1L_MASK, m, BIT3)
169 #define _MaskMiu1Req_MVD_R( m ) do { HAL_MIU_WriteRegBit(MIU_RQ3L_MASK, m, BIT4); HAL_MIU_Write…
170 #define _MaskMiu1Req_MVD_W( m ) do { HAL_MIU_WriteRegBit(MIU_RQ3L_MASK, m, BIT4); HAL_MIU_Write…
196 MS_BOOL HAL_MIU_WriteRegBit(MS_U32 u32RegAddr, MS_U8 u8Mask, MS_BOOL bEnable);