Lines Matching refs:mfe_reg
102 extern MFE_REG mfe_reg;
153 mfe_reg.reg_mfe_s_bspobuf_sadr_low = sadr_low; in SetObufAddr()
154 mfe_reg.reg_mfe_s_bspobuf_sadr_high = sadr_high; in SetObufAddr()
155 mfe_reg.reg_mfe_s_bspobuf_eadr_low = eadr_low; in SetObufAddr()
156 mfe_reg.reg_mfe_s_bspobuf_eadr_high = eadr_high; in SetObufAddr()
158 WriteRegMFE(0x3c, mfe_reg.reg3c, "", 0, ""); in SetObufAddr()
159 WriteRegMFE(0x3d, mfe_reg.reg3d, "", 0, ""); in SetObufAddr()
160 WriteRegMFE(0x3e, mfe_reg.reg3e, "", 0, ""); in SetObufAddr()
161 WriteRegMFE(0x3f, mfe_reg.reg3f, "", 0, ""); in SetObufAddr()
164 MFE_ASSERT(mfe_reg.reg_mfe_s_mvobuf_set_adr==0); in SetObufAddr()
165 mfe_reg.reg_mfe_s_bspobuf_set_adr = 1; in SetObufAddr()
166 WriteRegMFE(0x3b, mfe_reg.reg3b, "", 0, ""); in SetObufAddr()
167 mfe_reg.reg_mfe_s_bspobuf_set_adr = 0; // HW is write-one-clear in SetObufAddr()
172 mfe_reg.reg_mfe_g_irq_clr1 = 1; in ClearBsfFullIRQ()
173 WriteRegMFE(0x1d, mfe_reg.reg1d, "", 0, ""); in ClearBsfFullIRQ()
174 mfe_reg.reg_mfe_g_irq_clr1 = 0; // HW is write-one-clear in ClearBsfFullIRQ()
179 ReadRegMFE(0x1d, &mfe_reg.reg1d); in ClearIRQ()
181 case 0: mfe_reg.reg_mfe_g_irq_clr0 = 1; break; in ClearIRQ()
182 case 1: mfe_reg.reg_mfe_g_irq_clr1 = 1; break; in ClearIRQ()
183 case 2: mfe_reg.reg_mfe_g_irq_clr2 = 1; break; in ClearIRQ()
184 case 3: mfe_reg.reg_mfe_g_irq_clr3 = 1; break; in ClearIRQ()
185 case 4: mfe_reg.reg_mfe_g_irq_clr4 = 1; break; in ClearIRQ()
186 case 5: mfe_reg.reg_mfe_g_irq_clr5 = 1; break; in ClearIRQ()
187 case 6: mfe_reg.reg_mfe_g_irq_clr6 = 1; break; in ClearIRQ()
188 case 7: mfe_reg.reg_mfe_g_irq_clr7 = 1; break; in ClearIRQ()
190 WriteRegMFE(0x1d, mfe_reg.reg1d, "", 0, ""); in ClearIRQ()
192 case 0: mfe_reg.reg_mfe_g_irq_clr0 = 0; break; in ClearIRQ()
193 case 1: mfe_reg.reg_mfe_g_irq_clr1 = 0; break; in ClearIRQ()
194 case 2: mfe_reg.reg_mfe_g_irq_clr2 = 0; break; in ClearIRQ()
195 case 3: mfe_reg.reg_mfe_g_irq_clr3 = 0; break; in ClearIRQ()
196 case 4: mfe_reg.reg_mfe_g_irq_clr4 = 0; break; in ClearIRQ()
197 case 5: mfe_reg.reg_mfe_g_irq_clr5 = 0; break; in ClearIRQ()
198 case 6: mfe_reg.reg_mfe_g_irq_clr6 = 0; break; in ClearIRQ()
199 case 7: mfe_reg.reg_mfe_g_irq_clr7 = 0; break; in ClearIRQ()
206 mfe_reg.reg_mfe_g_frame_start_sw = 1; in Enable_HW()
208 WriteRegMFE(0x00, mfe_reg.reg00, "", 0, ""); in Enable_HW()
209 mfe_reg.reg_mfe_g_frame_start_sw = 0; // HW is write-one-clear in Enable_HW()
216 memset(&mfe_reg, 0, sizeof(MFE_REG)); // Initial in ResetAllRegs()
217 mfe_reg.reg_mfe_g_soft_rstz = 1; in ResetAllRegs()
218 WriteRegMFE(0x0, mfe_reg.reg00, "[%d] reg00", nRegWriteCount++, "SW reset 1"); in ResetAllRegs()
220 WriteRegMFE(0x3, mfe_reg.reg03, "[%d] reg03", nRegWriteCount++, "tbc_mode=0"); in ResetAllRegs()
221 WriteRegMFE(0x4, mfe_reg.reg04, "[%d] reg04", nRegWriteCount++, "er_bs mode threshold"); in ResetAllRegs()
222 mfe_reg.reg_mfe_g_inter_pref = 0x200; in ResetAllRegs()
223 WriteRegMFE(0x5, mfe_reg.reg05, "[%d] reg05", nRegWriteCount++, "inter prediction preference"); in ResetAllRegs()
225 WriteRegMFE(0x16, mfe_reg.reg16, "[%d] reg16", nRegWriteCount++, "clock gating=0"); in ResetAllRegs()
228 mfe_reg.reg_mfe_g_jpe_qfactor = 0x3; in ResetAllRegs()
229 mfe_reg.reg_mfe_g_viu_soft_rstz = 1; in ResetAllRegs()
230 WriteRegMFE(0x18, mfe_reg.reg18, "[%d] reg18", nRegWriteCount++, "JPE encode mode"); in ResetAllRegs()
233 WriteRegMFE(0x19, mfe_reg.reg19, "[%d] reg19", nRegWriteCount++, "value"); in ResetAllRegs()
234 WriteRegMFE(0x1a, mfe_reg.reg1a, "[%d] reg1a", nRegWriteCount++, "value"); in ResetAllRegs()
235 WriteRegMFE(0x1b, mfe_reg.reg1b, "[%d] reg1b", nRegWriteCount++, "value"); in ResetAllRegs()
238 mfe_reg.reg_mfe_s_me_ref_en_mode = 0x3; in ResetAllRegs()
239 WriteRegMFE(0x20, mfe_reg.reg20, "[%d] reg20", nRegWriteCount++, "ME partition setting"); in ResetAllRegs()
242 WriteRegMFE(0x21, mfe_reg.reg21, "[%d] reg21", nRegWriteCount++, "value"); in ResetAllRegs()
243 mfe_reg.reg_mfe_s_ime_mesr_max_addr = 0x5d; in ResetAllRegs()
244 WriteRegMFE(0x22, mfe_reg.reg22, "[%d] reg22", nRegWriteCount++, "me search range max depth"); in ResetAllRegs()
245 mfe_reg.reg_mfe_s_ime_mvx_max = 0x3e; in ResetAllRegs()
246 WriteRegMFE(0x23, mfe_reg.reg23, "[%d] reg23", nRegWriteCount++, "me mvx"); in ResetAllRegs()
247 mfe_reg.reg_mfe_s_ime_mvy_max = 0x1f; in ResetAllRegs()
248 WriteRegMFE(0x24, mfe_reg.reg24, "[%d] reg24", nRegWriteCount++, "me mvy"); in ResetAllRegs()
251 mfe_reg.reg_mfe_s_fme_pipeline_on = 0x0; // This is hw default value in ResetAllRegs()
252 WriteRegMFE(0x25, mfe_reg.reg25, "[%d] reg25", nRegWriteCount++, "FME"); in ResetAllRegs()
255 WriteRegMFE(0x26, mfe_reg.reg26, "[%d] reg26", nRegWriteCount++, "MBR: mbbits"); in ResetAllRegs()
256 WriteRegMFE(0x27, mfe_reg.reg27, "[%d] reg27", nRegWriteCount++, "MBR: frame qstep"); in ResetAllRegs()
257 WriteRegMFE(0x29, mfe_reg.reg29, "[%d] reg29", nRegWriteCount++, "264 qp-offset"); in ResetAllRegs()
258 mfe_reg.reg_mfe_s_mbr_qp_min = 0x1; in ResetAllRegs()
259 mfe_reg.reg_mfe_s_mbr_qp_max = 0x1d; in ResetAllRegs()
260 WriteRegMFE(0x2a, mfe_reg.reg2a, "[%d] reg2a", nRegWriteCount++, "QP min/max"); in ResetAllRegs()
261 mfe_reg.reg_mfe_s_mbr_qstep_min = 0x1f; in ResetAllRegs()
262 WriteRegMFE(0x6e, mfe_reg.reg6e, "[%d] reg6e", nRegWriteCount++, "QStep min"); in ResetAllRegs()
263 mfe_reg.reg_mfe_s_mbr_qstep_max = 0x3a0; in ResetAllRegs()
264 WriteRegMFE(0x6f, mfe_reg.reg6f, "[%d] reg6f", nRegWriteCount++, "QStep max"); in ResetAllRegs()
267 mfe_reg.reg_mfe_s_ieap_last_mode = 8; in ResetAllRegs()
268 mfe_reg.reg_mfe_s_ieap_ccest_en = 1; in ResetAllRegs()
269 mfe_reg.reg_mfe_s_ieap_ccest_thr = 3; in ResetAllRegs()
270 WriteRegMFE(0x2b, mfe_reg.reg2b, "[%d] reg2b", nRegWriteCount++, "ieap"); in ResetAllRegs()
273 WriteRegMFE(0x2c, mfe_reg.reg2c, "[%d] reg2c", nRegWriteCount++, "Last zigzag"); in ResetAllRegs()
276 WriteRegMFE(0x2d, mfe_reg.reg2d, "[%d] reg2d", nRegWriteCount, ""); in ResetAllRegs()
277 WriteRegMFE(0x2e, mfe_reg.reg2e, "[%d] reg2e", nRegWriteCount, ""); in ResetAllRegs()
278 WriteRegMFE(0x2f, mfe_reg.reg2f, "[%d] reg2f", nRegWriteCount, ""); in ResetAllRegs()
279 WriteRegMFE(0x30, mfe_reg.reg30, "[%d] reg30", nRegWriteCount, ""); in ResetAllRegs()
280 WriteRegMFE(0x31, mfe_reg.reg31, "[%d] reg31", nRegWriteCount, ""); in ResetAllRegs()
281 mfe_reg.reg_mfe_s_txip_wait_mode = 1; in ResetAllRegs()
282 WriteRegMFE(0x32, mfe_reg.reg32, "[%d] reg32", nRegWriteCount, ""); in ResetAllRegs()
283 WriteRegMFE(0x33, mfe_reg.reg33, "[%d] reg33", nRegWriteCount, ""); in ResetAllRegs()
284 WriteRegMFE(0x34, mfe_reg.reg34, "[%d] reg34", nRegWriteCount, ""); in ResetAllRegs()
287 WriteRegMFE(0x37, mfe_reg.reg37, "[%d] reg37", nRegWriteCount++, "MPEG4 MDC"); in ResetAllRegs()
288 WriteRegMFE(0x38, mfe_reg.reg38, "[%d] reg38", nRegWriteCount++, "MPEG4: vop_time_increment"); in ResetAllRegs()
289 WriteRegMFE(0x39, mfe_reg.reg39, "[%d] reg39", nRegWriteCount++, "value"); in ResetAllRegs()
290 mfe_reg.reg_mfe_s_mdc_h264_disable_dbf_idc = 2; in ResetAllRegs()
291 WriteRegMFE(0x3a, mfe_reg.reg3a, "[%d] reg3a", nRegWriteCount++, "value"); in ResetAllRegs()
294 WriteRegMFE(0x46, mfe_reg.reg46, "[FDC %d] reg46", nRegWriteCount++, "fdc bs"); in ResetAllRegs()
295 WriteRegMFE(0x47, mfe_reg.reg47, "[FDC %d] reg47", nRegWriteCount++, "fdc len"); in ResetAllRegs()
296 WriteRegMFE(0x48, mfe_reg.reg48, "[FDC %d] reg48", nRegWriteCount++, "fdc vld"); in ResetAllRegs()
298 WriteRegMFE(0x49, mfe_reg.reg49, "[Table %d] reg49", nRegWriteCount++, "table address"); in ResetAllRegs()
299 WriteRegMFE(0x4a, mfe_reg.reg4a, "[Table %d] reg4a", nRegWriteCount++, "table write data"); in ResetAllRegs()
302 WriteRegMFE(0x70, mfe_reg.reg70, "[%d] reg70", nRegWriteCount++, ""); in ResetAllRegs()
303 WriteRegMFE(0x71, mfe_reg.reg71, "[%d] reg71", nRegWriteCount++, ""); in ResetAllRegs()
304 WriteRegMFE(0x72, mfe_reg.reg72, "[%d] reg72", nRegWriteCount++, ""); in ResetAllRegs()
305 WriteRegMFE(0x73, mfe_reg.reg73, "[%d] reg73", nRegWriteCount++, ""); in ResetAllRegs()
310 mfe_reg.reg_mfe_g_debug_trig_mbx = STOP_MBX; in TestStopAtMb()
311 WriteRegMFE(0x71, mfe_reg.reg71, "[%d] reg71", 0, "reg_mfe_g_debug_trig_mbx"); in TestStopAtMb()
312 mfe_reg.reg_mfe_g_debug_trig_mby = STOP_MBY; in TestStopAtMb()
313 WriteRegMFE(0x72, mfe_reg.reg72, "[%d] reg72", 0, "reg_mfe_g_debug_trig_mby"); in TestStopAtMb()
314 mfe_reg.reg_mfe_s_txip_sng_mb = 1; in TestStopAtMb()
315 WriteRegMFE(0x2d, mfe_reg.reg2d, "[%d] reg2d", 0, "reg_mfe_s_txip_sng_mb=1"); in TestStopAtMb()
316 mfe_reg.reg_mfe_g_debug_trig_mode = 1; in TestStopAtMb()
317 mfe_reg.reg_mfe_g_debug_en = 1; in TestStopAtMb()
318 WriteRegMFE(0x73, mfe_reg.reg73, "[%d] reg73", 0, "reg_mfe_g_debug_trig_mode=1"); in TestStopAtMb()
319 mfe_reg.reg_mfe_g_debug_trig_cycle = 0; in TestStopAtMb()
320 WriteRegMFE(0x70, mfe_reg.reg70, "[%d] reg70", 0, "reg_mfe_g_debug_trig_cycle=0"); in TestStopAtMb()
325 mfe_reg.reg_mfe_s_txip_sng_set = 1; in TestStop()
326 WriteRegMFE(0x2d, mfe_reg.reg2d, "[%d] reg2d", 0, "reg_mfe_s_txip_sng_set=1"); in TestStop()
345 if (mfe_reg.reg_mfe_g_qmode==1) { // Q table in WriteQTable()
351 mfe_reg.reg_mfe_g_tbc_mode = 0; in WriteQTable()
352 WriteRegMFE(0x3, mfe_reg.reg03, "[%d] reg3", nRegWriteCount++, "tbc_mode=0"); in WriteQTable()
354 mfe_reg.reg48 = 0; in WriteQTable()
356 mfe_reg.reg_mfe_s_tbc_wdata =Table0[((i&0x7)<<3)|(i>>3)] in WriteQTable()
359 WriteRegMFE(0x4a, mfe_reg.reg4a, "[%d] reg4a", nRegWriteCount++, "table write data"); in WriteQTable()
360 mfe_reg.reg_mfe_s_tbc_rw = 1; in WriteQTable()
361 mfe_reg.reg_mfe_s_tbc_en = 1; in WriteQTable()
362 mfe_reg.reg_mfe_s_tbc_adr = i>>1; in WriteQTable()
363 WriteRegMFE(0x49, mfe_reg.reg49, "[%d] reg49", nRegWriteCount++, "table address"); in WriteQTable()
364 WriteRegMFE(0x48, mfe_reg.reg48, "[%d] reg48", nRegWriteCount++, "table write enable"); in WriteQTable()
391 mfe_reg.reg_mfe_s_tbc_wdata = Table1[((i&0x7)<<3)|(i>>3)] in WriteQTable()
394 … WriteRegMFE(0x4a, mfe_reg.reg4a, "[%d] reg4a", nRegWriteCount++, "table write data (inter)"); in WriteQTable()
395 mfe_reg.reg_mfe_s_tbc_rw = 1; in WriteQTable()
396 mfe_reg.reg_mfe_s_tbc_en = 1; in WriteQTable()
397 mfe_reg.reg_mfe_s_tbc_adr = (64+i)>>1; in WriteQTable()
398 WriteRegMFE(0x49, mfe_reg.reg49, "[%d] reg49", nRegWriteCount++, "table address"); in WriteQTable()
399 WriteRegMFE(0x48, mfe_reg.reg48, "[%d] reg48", nRegWriteCount++, "table write enable"); in WriteQTable()
400 mfe_reg.reg_mfe_s_tbc_en = 0; // HW is write-one-clear in WriteQTable()
426 mfe_reg.reg_mfe_g_tbc_mode = 1; in WriteQTable()
427 WriteRegMFE(0x3, mfe_reg.reg03, "[%d] reg03", nRegWriteCount++, "tbc_mode=1"); in WriteQTable()
435 mfe_reg.reg_mfe_g_tbc_mode = 0; in WriteQTable()
436 WriteRegMFE(0x3, mfe_reg.reg03, "[%d] reg03", nRegWriteCount++, "tbc_mode=0"); in WriteQTable()
438 mfe_reg.reg_mfe_g_tbc_mode = 1; in WriteQTable()
439 WriteRegMFE(0x3, mfe_reg.reg03, "[%d] reg03", nRegWriteCount++, "tbc_mode=1"); in WriteQTable()
445 if (mfe_reg.reg_mfe_g_qmode==1) { // Q table in WriteQTable()
474 mfe_reg.reg_mfe_s_tbc_en = 1; in WriteQTable()
475 WriteRegMFE(0x48, mfe_reg.reg48, "[%d] reg48", nRegWriteCount++, "table write enable"); in WriteQTable()
504 mfe_reg.reg_mfe_s_tbc_en = 1; in WriteQTable()
505 WriteRegMFE(0x48, mfe_reg.reg48, "[%d] reg48", nRegWriteCount++, "table write enable"); in WriteQTable()
506 mfe_reg.reg_mfe_s_tbc_en = 0; // HW is write-one-clear in WriteQTable()
573 mfe_reg.reg46 = 0; in PutFDC()
574 mfe_reg.reg47 = 0; in PutFDC()
575 mfe_reg.reg48 = 0; in PutFDC()
577 mfe_reg.reg_mfe_s_fdc_bs_count = nTotalRound-1; // Count from 0 in PutFDC()
578 WriteRegMFE(0x47, mfe_reg.reg47, "[FDC %d] reg47", nRegWriteNum++, "fdc round count"); in PutFDC()
586 mfe_reg.reg_mfe_s_fdc_bs = val; in PutFDC()
587 mfe_reg.reg_mfe_s_fdc_bs_len = 15; in PutFDC()
588 mfe_reg.reg_mfe_s_fdc_bs_vld = 1; in PutFDC()
589 WriteRegMFE(0x46, mfe_reg.reg46, "[FDC %d] reg46", nRegWriteNum++, "fdc bs"); in PutFDC()
590 WriteRegMFE(0x47, mfe_reg.reg47, "[FDC %d] reg47", nRegWriteNum++, "fdc len"); in PutFDC()
591 WriteRegMFE(0x48, mfe_reg.reg48, "[FDC %d] reg48", nRegWriteNum++, "fdc vld"); in PutFDC()
592 mfe_reg.reg_mfe_s_fdc_bs_vld = 0; // HW is write-one-clear in PutFDC()
628 mfe_reg.reg_mfe_s_fdc_bs = val; in PutFDC()
629 mfe_reg.reg_mfe_s_fdc_bs_len = bit_len; in PutFDC()
630 mfe_reg.reg_mfe_s_fdc_bs_vld = 1; in PutFDC()
631 WriteRegMFE(0x46, mfe_reg.reg46, "[FDC %d] reg46", nRegWriteNum++, "fdc bs"); in PutFDC()
632 WriteRegMFE(0x47, mfe_reg.reg47, "[FDC %d] reg47", nRegWriteNum++, "fdc len"); in PutFDC()
633 WriteRegMFE(0x48, mfe_reg.reg48, "[FDC %d] reg48", nRegWriteNum++, "fdc vld"); in PutFDC()
634 mfe_reg.reg_mfe_s_fdc_bs_vld = 0; // HW is write-one-clear in PutFDC()