Lines Matching refs:HAL_HWI2C_WriteRegBit
317 MS_BOOL HAL_HWI2C_WriteRegBit(MS_U32 u32RegAddr, MS_U8 u8Mask, MS_BOOL bEnable) in HAL_HWI2C_WriteRegBit() function
371 return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u32PortOffset, _MIIC_CFG_EN_INT, bEnable); in HAL_HWI2C_EnINT()
384 return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u32PortOffset, _MIIC_CFG_EN_DMA, bEnable); in HAL_HWI2C_EnDMA()
397 return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u32PortOffset, _MIIC_CFG_EN_CLKSTR, bEnable); in HAL_HWI2C_EnClkStretch()
411 return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u32PortOffset, _MIIC_CFG_EN_TMTINT, bEnable);
425 return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u32PortOffset, _MIIC_CFG_EN_FILTER, bEnable); in HAL_HWI2C_EnFilter()
438 return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u32PortOffset, _MIIC_CFG_EN_PUSH1T, bEnable); in HAL_HWI2C_EnPushSda()
457 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u32PortOffset, _DMA_CFG_INTEN, bEnable); in HAL_HWI2C_DMA_SetINT()
470 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u32PortOffset, _DMA_CFG_RESET, bReset); in HAL_HWI2C_DMA_Reset()
483 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u32PortOffset, _DMA_CFG_MIURST, bReset); in HAL_HWI2C_DMA_MiuReset()
501 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u32PortOffset, _DMA_CFG_MIUPRI, bHighPri); in HAL_HWI2C_DMA_SetMiuPri()
538 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL_TRIG+u32PortOffset, _DMA_CTL_TRIG, TRUE); in HAL_HWI2C_DMA_Trigger()
552 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_RETRIG, TRUE);
569 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_TXNOSTOP, bTxNoStop); in HAL_HWI2C_DMA_SetTxfrStop()
603 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_RDWTCMD, bRdWrt); in HAL_HWI2C_DMA_SetRdWrt()
621 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_MIUCHSEL, bMiuCh1); in HAL_HWI2C_DMA_SetMiuChannel()
634 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_TXR+u32PortOffset, _DMA_TXR_DONE, TRUE); in HAL_HWI2C_DMA_TxfrDone()
784 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_SLVCFG+u32PortOffset, _DMA_10BIT_MODE, b10BitMode); in HAL_HWI2C_DMA_SetAddrMode()
1070 bRet &= HAL_HWI2C_WriteRegBit(CHIP_REG_ALLPADIN, CHIP_ALLPAD_IN, FALSE); in HAL_HWI2C_Init_Chip()
1097 return HAL_HWI2C_WriteRegBit(REG_HWI2C_ADV_CTL+u32PortOffset, _ADV_DMA_PASS_INT, bEnable); in HAL_HWI2C_DMA_Pass_IntEnable()
1121 return HAL_HWI2C_WriteRegBit(REG_HWI2C_ADV_CTL+u32PortOffset, _ADV_START2B_DELAY, bEnable); in HAL_HWI2C_Start2ByteDelay_Enable()
1133 return HAL_HWI2C_WriteRegBit(REG_HWI2C_ADV_CTL+u32PortOffset, _ADV_BYTE2BYTE_DELAY, bEnable); in HAL_HWI2C_Byte2ByteDelay_Enable()
1524 …HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CMDDAT7+u32PortOffset, _DMA_CMDDAT7_MSK, TRUE); //(### REVIEW … in HAL_HWI2C_Start()
1526 HAL_HWI2C_WriteRegBit(REG_HWI2C_CMD_START+u32PortOffset, _CMD_START, TRUE); in HAL_HWI2C_Start()
1537 HAL_HWI2C_WriteRegBit(REG_HWI2C_CMD_START+u32PortOffset, _CMD_START, TRUE); in HAL_HWI2C_Start()
1558 HAL_HWI2C_WriteRegBit(REG_HWI2C_CMD_STOP+u32PortOffset, _CMD_STOP, TRUE); in HAL_HWI2C_Stop()
1735 return HAL_HWI2C_WriteRegBit(REG_HWI2C_INT_CTL+u32PortOffset, _INT_CTL, TRUE); in HAL_HWI2C_Clear_INT()
1749 return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u32PortOffset, _MIIC_CFG_RESET, bReset); in HAL_HWI2C_Reset()