1531 void _mhal_mhl_SetECbusStateChangeInterrupt(MS_BOOL bEnableFlag)  in _mhal_mhl_SetECbusStateChangeInterrupt()  argument
1533     if(bEnableFlag)  in _mhal_mhl_SetECbusStateChangeInterrupt()
1555 void _mhal_mhl_SetEMSCReceiveInterrupt(MS_BOOL bEnableFlag)  in _mhal_mhl_SetEMSCReceiveInterrupt()  argument
1557     W2BYTEMSK(REG_MHL_ECBUS_36, bEnableFlag? 0: BIT(12), BIT(12)); // eMSC receive int mask  in _mhal_mhl_SetEMSCReceiveInterrupt()
1571 void _mhal_mhl_CbusConnectCheckEnable(MS_BOOL bEnableFlag)  in _mhal_mhl_CbusConnectCheckEnable()  argument
1573 …W2BYTEMSK(REG_PM_MHL_CBUS_0B, bEnableFlag? MHL_CBUS_CONNECT_CHECK_VALUE: 0, BMASK(15:0)); // [15:0…  in _mhal_mhl_CbusConnectCheckEnable()
1586 void _mhal_mhl_ECbusEnableSetting(MS_BOOL bEnableFlag)  in _mhal_mhl_ECbusEnableSetting()  argument
1588     W2BYTEMSK(REG_MHL_ECBUS_PHY_4D, bEnableFlag? 0: BIT(0), BIT(0)); // ECbus PLL pd  in _mhal_mhl_ECbusEnableSetting()
1590     W2BYTEMSK(REG_MHL_ECBUS_PHY_57, bEnableFlag? BIT(3): BIT(2), BMASK(3:2)); //    in _mhal_mhl_ECbusEnableSetting()
1591     W2BYTEMSK(REG_MHL_ECBUS_PHY_6F, bEnableFlag? BIT(8): 0, BIT(8)); // ECbus clock detect  in _mhal_mhl_ECbusEnableSetting()
1592     W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, bEnableFlag? 0: BIT(13), BIT(13));  in _mhal_mhl_ECbusEnableSetting()
1593     W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, bEnableFlag? 0: BIT(13), BIT(13));  in _mhal_mhl_ECbusEnableSetting()
1595     if(bEnableFlag)  in _mhal_mhl_ECbusEnableSetting()
1615 void _mhal_mhl_ECbusDmuxEnable(MS_BOOL bEnableFlag)  in _mhal_mhl_ECbusDmuxEnable()  argument
1617     W2BYTEMSK(REG_MHL_ECBUS_PHY_4F, bEnableFlag? BIT(3): 0, BIT(3)); // [3]: Enable ECbus dmux  in _mhal_mhl_ECbusDmuxEnable()
1679 void _mhal_mhl_Version3PhyEnable(MS_U8 ucCbusSelect, MS_BOOL bEnableFlag)  in _mhal_mhl_Version3PhyEnable()  argument
1687 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_60_L, bEnableFlag? BMASK(10:8): 0, BMASK(10:8)); // [8]: MHL3 engin…  in _mhal_mhl_Version3PhyEnable()
1688 …W2BYTEMSK(REG_COMBO_PHY0_P0_73_L, bEnableFlag? MHL_EQ_30_SETTING_VALUE: MHL_EQ_20_SETTING_VALUE, B…  in _mhal_mhl_Version3PhyEnable()
1689                 W2BYTEMSK(REG_COMBO_PHY0_P0_60_L, bEnableFlag? 0: BIT(5), BIT(5));  in _mhal_mhl_Version3PhyEnable()
1699 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_60_L, bEnableFlag? BMASK(10:8): 0, BMASK(10:8)); // [8]: MHL3 engin…  in _mhal_mhl_Version3PhyEnable()
1700 …W2BYTEMSK(REG_COMBO_PHY0_P1_73_L, bEnableFlag? MHL_EQ_30_SETTING_VALUE: MHL_EQ_20_SETTING_VALUE, B…  in _mhal_mhl_Version3PhyEnable()
1701                 W2BYTEMSK(REG_COMBO_PHY0_P1_60_L, bEnableFlag? 0: BIT(5), BIT(5));  in _mhal_mhl_Version3PhyEnable()
1711 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_60_L, bEnableFlag? BMASK(10:8): 0, BMASK(10:8)); // [8]: MHL3 engin…  in _mhal_mhl_Version3PhyEnable()
1712 …W2BYTEMSK(REG_COMBO_PHY0_P2_73_L, bEnableFlag? MHL_EQ_30_SETTING_VALUE: MHL_EQ_20_SETTING_VALUE, B…  in _mhal_mhl_Version3PhyEnable()
1713                 W2BYTEMSK(REG_COMBO_PHY0_P2_60_L, bEnableFlag? 0: BIT(5), BIT(5));  in _mhal_mhl_Version3PhyEnable()
1723 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_60_L, bEnableFlag? BMASK(10:8): 0, BMASK(10:8)); // [8]: MHL3 engin…  in _mhal_mhl_Version3PhyEnable()
1724 …W2BYTEMSK(REG_COMBO_PHY0_P3_73_L, bEnableFlag? MHL_EQ_30_SETTING_VALUE: MHL_EQ_20_SETTING_VALUE, B…  in _mhal_mhl_Version3PhyEnable()
1725                 W2BYTEMSK(REG_COMBO_PHY0_P3_60_L, bEnableFlag? 0: BIT(5), BIT(5));  in _mhal_mhl_Version3PhyEnable()