Lines Matching refs:MHalHdcpRegMaskWrite
184 void MHalHdcpRegMaskWrite(MS_U32 bank, MS_U16 address, MS_U16 reg_mask, MS_U16 reg_data) in MHalHdcpRegMaskWrite() function
221 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0001, 0x8000, 0x8000); // Enable HDCP encryption in MHal_HDCP_HDCP14TxInitHdcp()
222 …MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x001C, 0x0000); //[4]: 1: km new mode; 0: km… in MHal_HDCP_HDCP14TxInitHdcp()
238 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x000F, 0x000C); in MHal_HDCP_HDCP14TxSetAuthPass()
247 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x0008, 0x0008); in MHal_HDCP_HDCP14TxEnableENC_EN()
249 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x0008, 0x0000); in MHal_HDCP_HDCP14TxEnableENC_EN()
260 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0001, 0x0100, 0x0100); in MHal_HDCP_HDCP14TxProcessAn()
261 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x0002, 0x0002); in MHal_HDCP_HDCP14TxProcessAn()
262 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x0002, 0x0000); in MHal_HDCP_HDCP14TxProcessAn()
274 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0001, 0x0100, 0x0000); in MHal_HDCP_HDCP14TxProcessAn()
334 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0001, 0x0E00, u8Mode << 8); in MHal_HDCP_HDCP14TxConfigMode()
398 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x000F, 0x0000); in MHal_HDCP_HDCP14TxProcessR0()
399 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x000F, 0x0001); in MHal_HDCP_HDCP14TxProcessR0()
400 MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, 0x0002, 0x000F, 0x0000); in MHal_HDCP_HDCP14TxProcessR0()
472 …MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x11, bEnable ? 0x11 : 0x00); /… in MHal_HDCP_HDCP2TxInit()
475 … MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x02, 0x02); //reset hdcp22 FSM in MHal_HDCP_HDCP2TxInit()
476 MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x02, 0x00); in MHal_HDCP_HDCP2TxInit()
484 …MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x04, bEnable ? 0x04 : 0x00); /… in MHal_HDCP_HDCP2TxEnableEncrypt()
485 …MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x08, bEnable ? 0x08 : 0x00); /… in MHal_HDCP_HDCP2TxEnableEncrypt()
520 …MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK + u16BKOffset, 0x0000, 0x04, bEnable ? 0x04 : 0x00); /… in MHal_HDCP_HDCP2TxSetAuthPass()
554 …MHalHdcpRegMaskWrite(DEF_HDCP14_TX_REG_BANK, REG_HDCP14_TX_02_L, BIT(3), u32SetStatus? BIT(3): 0);… in MHal_HDCP_HDCP1TxEncrytionStatus()
572 …MHalHdcpRegMaskWrite(DEF_HDCP22_TX_REG_BANK, REG_HDCP22_TX_00_L, BIT(3), u32SetStatus? BIT(3): 0);… in MHal_HDCP_HDCP2TxEncrytionStatus()
590 …MHalHdcpRegMaskWrite(DEF_HDMITX_PHY_REG_BANK, REG_HDMITX_PHY_39_L, 0xFFFF, u32SetStatus? 0xF000: 0… in MHal_HDCP_HDCPTxHDMIStatus()
591 …MHalHdcpRegMaskWrite(DEF_HDMITX_PHY_REG_BANK, REG_HDMITX_PHY_2E_L, 0xE800, u32SetStatus? 0xE800: 0… in MHal_HDCP_HDCPTxHDMIStatus()