Lines Matching refs:TSP_CLKGEN0_REG
213 #define TSP_CLKGEN0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x1600UL + ((addr)<<2UL)))) macro
1869 …TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_TS4) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_TS4) & ~(REG_CLKGEN0_TSN_C… in HAL_TSP_TsOutPadCfg()
2074 …u32data = TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_… in HAL_TSP_SelPad_ClkInv()
2076 TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) = u32data; in HAL_TSP_SelPad_ClkInv()
2079 …u32data = TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_… in HAL_TSP_SelPad_ClkInv()
2081 TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) = u32data; in HAL_TSP_SelPad_ClkInv()
2084 …u32data = TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK2) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK… in HAL_TSP_SelPad_ClkInv()
2086 TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK2) = u32data; in HAL_TSP_SelPad_ClkInv()
3194 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS0_SHIFT) & REG_CLKGEN0… in HAL_TSP_GetTSIF_Status()
3201 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS1_SHIFT) & REG_CLKGEN0… in HAL_TSP_GetTSIF_Status()
3208 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK2) >> REG_CLKGEN0_TSN_CLK_TS2_SHIFT) & REG_CLKGEN… in HAL_TSP_GetTSIF_Status()
3377 … return (TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L) | TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H)); in HAL_TSP_GetSTCSynth()
3379 … return (TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_L) | TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_H)); in HAL_TSP_GetSTCSynth()
3396 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_SetSTCSynth()
3400 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L) = (MS_U16)(u32Sync & 0xFFFF); in HAL_TSP_SetSTCSynth()
3401 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H) = (MS_U16)((u32Sync >> 16UL) & 0xFFFF); in HAL_TSP_SetSTCSynth()
3404 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_EN; in HAL_TSP_SetSTCSynth()
3405 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_EN; in HAL_TSP_SetSTCSynth()
3406 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_EN; in HAL_TSP_SetSTCSynth()
3410 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_SetSTCSynth()
3413 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH1) &= ~REG_CLKGEN0_STC1_CW_SEL; in HAL_TSP_SetSTCSynth()
3414 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_L) = (MS_U16)(u32Sync & 0xFFFF); in HAL_TSP_SetSTCSynth()
3415 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_H) = (MS_U16)((u32Sync >> 16UL) & 0xFFFF); in HAL_TSP_SetSTCSynth()
3416 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH1) &= ~REG_CLKGEN0_STC1_CW_EN; in HAL_TSP_SetSTCSynth()
3417 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH1) |= REG_CLKGEN0_STC1_CW_EN; in HAL_TSP_SetSTCSynth()
3418 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH1) &= ~REG_CLKGEN0_STC1_CW_EN; in HAL_TSP_SetSTCSynth()
3419 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH1) |= REG_CLKGEN0_STC1_CW_SEL; in HAL_TSP_SetSTCSynth()
5840 _u16ClkgenRegArray[0x05] = TSP_CLKGEN0_REG(0x05); in HAL_TSP_SaveRegs()
5841 _u16ClkgenRegArray[0x70] = TSP_CLKGEN0_REG(0x70); in HAL_TSP_SaveRegs()
5842 _u16ClkgenRegArray[0x25] = TSP_CLKGEN0_REG(0x25); in HAL_TSP_SaveRegs()
5843 _u16ClkgenRegArray[0x28] = TSP_CLKGEN0_REG(0x28); in HAL_TSP_SaveRegs()
5844 _u16ClkgenRegArray[0x29] = TSP_CLKGEN0_REG(0x29); in HAL_TSP_SaveRegs()
5880 TSP_CLKGEN0_REG(0x05) = _u16ClkgenRegArray[0x05]; in HAL_TSP_RestoreRegs()
5881 TSP_CLKGEN0_REG(0x70) = _u16ClkgenRegArray[0x70]; in HAL_TSP_RestoreRegs()
5882 TSP_CLKGEN0_REG(0x25) = _u16ClkgenRegArray[0x25]; in HAL_TSP_RestoreRegs()
5883 TSP_CLKGEN0_REG(0x28) = _u16ClkgenRegArray[0x28]; in HAL_TSP_RestoreRegs()
5884 TSP_CLKGEN0_REG(0x29) = _u16ClkgenRegArray[0x29]; in HAL_TSP_RestoreRegs()