Lines Matching refs:u16RegMask

596     MS_U16 u16Reg, u16RegMask, u16RegShift;  in HAL_TSO_SelPad()  local
634 u16RegMask = REG_TOP_TS0_CONFIG_MASK; in HAL_TSO_SelPad()
646 u16RegMask = REG_TOP_TS1_CONFIG_MASK; in HAL_TSO_SelPad()
658 u16RegMask = REG_TOP_TS2_CONFIG_MASK; in HAL_TSO_SelPad()
670 u16RegMask = REG_TOP_TS3_CONFIG_MASK; in HAL_TSO_SelPad()
682 u16RegMask = REG_TOP_TS4_CFG_MASK; in HAL_TSO_SelPad()
700 TSP_TOP_REG(u16Reg) = (TSP_TOP_REG(u16Reg) & ~u16RegMask) | u16data; in HAL_TSO_SelPad()
709 MS_U16 u16Reg, u16RegMask, u16RegShift; in HAL_TSO_Set_InClk() local
719 u16RegMask = REG_CLKGEN0_TSO_IN_MASK; in HAL_TSO_Set_InClk()
721 u16value = TSO_CLKGEN0_REG(u16Reg) & ~u16RegMask; in HAL_TSO_Set_InClk()
725 u16RegMask = REG_CLKGEN2_TSO1_IN_MASK; in HAL_TSO_Set_InClk()
727 u16value = TSO_CLKGEN2_REG(u16Reg) & ~u16RegMask; in HAL_TSO_Set_InClk()
731 u16RegMask = REG_CLKGEN2_TSO2_IN_MASK; in HAL_TSO_Set_InClk()
733 u16value = TSO_CLKGEN2_REG(u16Reg) & ~u16RegMask; in HAL_TSO_Set_InClk()
737 u16RegMask = REG_CLKGEN2_MMT_IN_MASK; in HAL_TSO_Set_InClk()
739 u16value = TSO_CLKGEN2_REG(u16Reg) & ~u16RegMask; in HAL_TSO_Set_InClk()
785 MS_U16 u16Reg, u16RegMask, u16RegShift; in HAL_TSO_GetInputTSIF_Status() local
794 u16RegMask = REG_TSP5_TSOIN_MUX_MASK; in HAL_TSO_GetInputTSIF_Status()
799 u16RegMask = REG_TSP5_TSOIN_MUX_MASK; in HAL_TSO_GetInputTSIF_Status()
804 u16RegMask = REG_TSP5_TSOIN_MUX_MASK; in HAL_TSO_GetInputTSIF_Status()
809 u16RegMask = REG_TSP5_MMT_MUX_MASK; in HAL_TSO_GetInputTSIF_Status()
816 *pu16Pad = (TSP_TSP5_REG(u16Reg) & (u16RegMask << u16RegShift)) >> u16RegShift; in HAL_TSO_GetInputTSIF_Status()