Lines Matching refs:u16RegShift
563 MS_U16 u16Reg, u16RegMask, u16RegShift; in HAL_TSO_SelPad() local
570 u16RegShift = REG_TSP5_TSOIN0_MUX_SHIFT; in HAL_TSO_SelPad()
573 u16RegShift = REG_TSP5_TSOIN1_MUX_SHIFT; in HAL_TSO_SelPad()
576 u16RegShift = REG_TSP5_TSOIN2_MUX_SHIFT; in HAL_TSO_SelPad()
658 …REG(REG_TSP5_TSOIN_MUX) & ~(REG_TSP5_TSOIN_MUX_MASK << u16RegShift)) | (u16InPadSel << u16RegShift… in HAL_TSO_SelPad()
667 …) = (TSP_TSP5_REG(REG_TSP5_TSOIN_MUX) & ~(REG_TSP5_TSOIN_MUX_MASK)) | (u16InPadSel << u16RegShift); in HAL_TSO_SelPad()
674 MS_U16 u16Reg, u16RegMask, u16RegShift; in HAL_TSO_Set_InClk() local
685 u16RegShift = REG_CLKGEN0_TSO_IN_SHIFT; in HAL_TSO_Set_InClk()
691 u16RegShift = REG_CLKGEN2_TSO1_IN_SHIFT; in HAL_TSO_Set_InClk()
697 u16RegShift = REG_CLKGEN2_TSO2_IN_SHIFT; in HAL_TSO_Set_InClk()
708 u16value |= ((REG_CLKGEN2_TSO1_IN_DISABLE << u16RegShift) & 0xFFFFUL); in HAL_TSO_Set_InClk()
717 u16value |= (u16ClkSel << u16RegShift); in HAL_TSO_Set_InClk()
720 u16value |= ((REG_CLKGEN2_TSO1_IN_INVERT << u16RegShift) & 0xFFFFUL); in HAL_TSO_Set_InClk()
742 MS_U16 u16Reg, u16RegMask, u16RegShift; in HAL_TSO_GetInputTSIF_Status() local
752 u16RegShift = REG_TOP_TSO_MUX_SHIFT; in HAL_TSO_GetInputTSIF_Status()
757 u16RegShift = REG_TOP_TSO1_MUX_SHIFT; in HAL_TSO_GetInputTSIF_Status()
762 u16RegShift = REG_TOP_TSO2_MUX_SHIFT; in HAL_TSO_GetInputTSIF_Status()
768 *pu16Pad = (TSP_TOP_REG(u16Reg) & u16RegMask) >> u16RegShift; in HAL_TSO_GetInputTSIF_Status()