Lines Matching refs:TSO1_REG
145 #define TSO1_REG(addr) (*((volatile MS_U16*)(_virtTSORegBase + REG_CTRL_BASE_TSO1 + ((… macro
1810 _u16TSORegArray[1][0x00] = TSO1_REG(0x00); in HAL_TSO_SaveRegs()
1811 _u16TSORegArray[1][0x10] = TSO1_REG(0x10); in HAL_TSO_SaveRegs()
1812 _u16TSORegArray[1][0x14] = TSO1_REG(0x14); in HAL_TSO_SaveRegs()
1816 _u16TSORegArray[1][u32ii] = TSO1_REG(u32ii); in HAL_TSO_SaveRegs()
1821 _u16TSORegArray[1][u32ii] = TSO1_REG(u32ii); in HAL_TSO_SaveRegs()
1877 TSO1_REG(0x00) = _u16TSORegArray[1][0x00]; in HAL_TSO_RestoreRegs()
1881 TSO1_REG(u32temp+0x10) = _u16TSORegArray[1][u32temp+0x10]; in HAL_TSO_RestoreRegs()
1885 TSO1_REG(0x18) = _u16TSORegArray[1][0x18]; in HAL_TSO_RestoreRegs()
1886 TSO1_REG(0x19) = _u16TSORegArray[1][0x19]; in HAL_TSO_RestoreRegs()
1887 TSO1_REG(0x1a) = _u16TSORegArray[1][0x1a]; in HAL_TSO_RestoreRegs()
1888 TSO1_REG(0x1b) = _u16TSORegArray[1][0x1b] & ~TSO_SVQ_TX_CFG_SVQ_EN; //disable SVQ fisr in HAL_TSO_RestoreRegs()
1893 TSO1_REG(u32temp+0x28) = _u16TSORegArray[1][u32temp+0x28]; in HAL_TSO_RestoreRegs()
1894 TSO1_REG(u32temp+0x29) = _u16TSORegArray[1][u32temp+0x29]; in HAL_TSO_RestoreRegs()
1895 TSO1_REG(u32temp+0x2a) = _u16TSORegArray[1][u32temp+0x2a]; in HAL_TSO_RestoreRegs()
1896 …TSO1_REG(u32temp+0x2b) = _u16TSORegArray[1][u32temp+0x2b] & ~TSO_SVQ_TX_CFG_SVQ_EN; //disable SVQ… in HAL_TSO_RestoreRegs()
1901 TSO1_REG(u32ii) = _u16TSORegArray[1][u32ii]; in HAL_TSO_RestoreRegs()
1907 TSO1_REG(0x1b) |= TSO_SVQ_TX_CFG_TX_RESET; in HAL_TSO_RestoreRegs()
1908 TSO1_REG(0x1b) &= ~TSO_SVQ_TX_CFG_TX_RESET; in HAL_TSO_RestoreRegs()
1909 TSO1_REG(0x2b) |= TSO_SVQ_TX_CFG_TX_RESET; in HAL_TSO_RestoreRegs()
1910 TSO1_REG(0x2b) &= ~TSO_SVQ_TX_CFG_TX_RESET; in HAL_TSO_RestoreRegs()
1911 TSO1_REG(0x2f) |= TSO_SVQ_TX_CFG_TX_RESET; in HAL_TSO_RestoreRegs()
1912 TSO1_REG(0x2f) &= ~TSO_SVQ_TX_CFG_TX_RESET; in HAL_TSO_RestoreRegs()
1914 TSO1_REG(0x1b) |= TSO_SVQ_TX_CFG_SVQ_EN; in HAL_TSO_RestoreRegs()