203 #define TSP_CLKGEN0_REG(addr)       (*((volatile MS_U16*)(_u32RegBase + 0x1600 + ((addr)<<2))))  macro
1864         TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLKTS4) =  in HAL_TSP_TsOutPadCfg()
1865 …(TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLKTS4) & ~(REG_CLKGEN0_TSN_CLK_MASK<<REG_CLKGEN0_TSN_CLK_TS4_SHI…  in HAL_TSP_TsOutPadCfg()
2040 …u32data = TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_…  in HAL_TSP_SelPad_ClkInv()
2042             TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) = u32data;  in HAL_TSP_SelPad_ClkInv()
2045 …u32data = TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< REG_CLKGEN0_TSN_CLK_…  in HAL_TSP_SelPad_ClkInv()
2047             TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) = u32data;  in HAL_TSP_SelPad_ClkInv()
2957 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS0_SHIFT) & REG_CLKGEN0_T…  in HAL_TSP_GetTSIF_Status()
2964 …*pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS1_SHIFT) & REG_CLKGEN0_T…  in HAL_TSP_GetTSIF_Status()
3083     TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~u32value;  in HAL_TSP_Stc_ctrl()
3088     TSP_CLKGEN0_REG(u32value) = (MS_U16)(u32Sync & 0xFFFF);  in HAL_TSP_Stc_ctrl()
3090     TSP_CLKGEN0_REG(u32value) = (MS_U16)(u32Sync >> 16);  in HAL_TSP_Stc_ctrl()
3094     TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~u32value;  in HAL_TSP_Stc_ctrl()
3095     TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= u32value;  in HAL_TSP_Stc_ctrl()
3096     TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~u32value;  in HAL_TSP_Stc_ctrl()
3101     TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= u32value;  in HAL_TSP_Stc_ctrl()
3120     u32sync = (MS_U32)TSP_CLKGEN0_REG(u32value);  in HAL_TSP_GetSTCSynth()
3122     u32sync |= (((MS_U32)TSP_CLKGEN0_REG(u32value)) << 16);  in HAL_TSP_GetSTCSynth()