100 REG_FIQ*               _REGFIQ    = NULL;  variable
135     _REGFIQ = (REG_FIQ*)(_u32RegBase + FQ_REG_CTRL_BASE);  in HAL_FQ_SetBank()
164     FQ32_W(&(_REGFIQ[u32FQEng].str2mi_head), MIU_FQ(u32StartAddr) & FIQ_STR2MI2_ADDR_MASK);  in HAL_FQ_PVR_SetBuf()
165     FQ32_W(&(_REGFIQ[u32FQEng].str2mi_tail), MIU_FQ(u32EndAddr) & FIQ_STR2MI2_ADDR_MASK);  in HAL_FQ_PVR_SetBuf()
166     FQ32_W(&(_REGFIQ[u32FQEng].str2mi_mid), MIU_FQ(u32StartAddr) & FIQ_STR2MI2_ADDR_MASK);  in HAL_FQ_PVR_SetBuf()
171     FQ32_W(&(_REGFIQ[u32FQEng].rush_addr), MIU_FQ(u32RushAddr) & FIQ_STR2MI2_ADDR_MASK);  in HAL_FQ_PVR_SetRushAddr()
177 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config…  in HAL_FQ_PVR_Start()
178 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config…  in HAL_FQ_PVR_Start()
181 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config…  in HAL_FQ_PVR_Start()
186 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config…  in HAL_FQ_PVR_Stop()
191 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config…  in HAL_FQ_Rush_Enable()
192 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config…  in HAL_FQ_Rush_Enable()
199 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config11), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_confi…  in HAL_FQ_Bypass()
203 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config11), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_confi…  in HAL_FQ_Bypass()
211 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config…  in HAL_FQ_SWReset()
215 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config…  in HAL_FQ_SWReset()
223 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config…  in HAL_FQ_AddrMode()
227 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config…  in HAL_FQ_AddrMode()
253 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config11), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_confi…  in HAL_FQ_SkipRushData()
254 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config11), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_confi…  in HAL_FQ_SkipRushData()
259 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config16),  _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_conf…  in HAL_FQ_INT_Enable()
264 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config16), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_confi…  in HAL_FQ_INT_Disable()
269     return _HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config16)) & FIQ_CFG16_INT_STATUS_MASK;  in HAL_FQ_INT_GetHW()
274 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config16), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_confi…  in HAL_FQ_INT_ClrHW()