Lines Matching refs:u32Eng
293 static MS_U32 _Adjust_PVR_WritePtr(MS_U32 u32Eng, MS_U32 u32WritePtr) in _Adjust_PVR_WritePtr() argument
295 if(_stPvrBuf[u32Eng].bPA2KSEG1_Mapping != TRUE) in _Adjust_PVR_WritePtr()
300 if (_stPvrBuf[u32Eng].u32Start == 0) in _Adjust_PVR_WritePtr()
305 …if (!((E_TSP_PVR_PVRENG_START <= u32Eng) && (E_TSP_PVR_PVRENG_END > u32Eng))) // PVR Eng number ch… in _Adjust_PVR_WritePtr()
310 if( _stPvrBuf[u32Eng].bOverWrite ) // If PVR buffer in OverWrite state in _Adjust_PVR_WritePtr()
318 if(*((MS_U64*)(MsOS_PA2KSEG1(_stPvrBuf[u32Eng].u32Start)))!= PVR_NON_OVERWRITE) in _Adjust_PVR_WritePtr()
320 _stPvrBuf[u32Eng].bOverWrite = TRUE; // Set PVR buffer to OverWrite state in _Adjust_PVR_WritePtr()
325 if( u32WritePtr >= _stPvrBuf[u32Eng].u32End ) in _Adjust_PVR_WritePtr()
328 u32WritePtr = _stPvrBuf[u32Eng].u32Start; in _Adjust_PVR_WritePtr()
5200 TSP_SRC_SEQ HAL_TSP_Eng2PktDmx_Mapping(MS_U32 u32Eng) in HAL_TSP_Eng2PktDmx_Mapping() argument
5202 switch(u32Eng) in HAL_TSP_Eng2PktDmx_Mapping()
5303 MS_U32 HAL_TSP_PidFltDstMapping(TSP_PIDFLT_DST eDstType, MS_U32 u32Eng) in HAL_TSP_PidFltDstMapping() argument
5307 switch(u32Eng) in HAL_TSP_PidFltDstMapping()
5320 switch(u32Eng) in HAL_TSP_PidFltDstMapping()
5337 switch(u32Eng) in HAL_TSP_PidFltDstMapping()
6848 MS_BOOL HAL_TSP_CAPVR_SPSEnable(MS_U32 u32Eng, MS_U16 u16CaPvrMode, MS_BOOL bEnable) in HAL_TSP_CAPVR_SPSEnable() argument
6852 switch(u32Eng) in HAL_TSP_CAPVR_SPSEnable()
6872 switch(u32Eng) in HAL_TSP_CAPVR_SPSEnable()
6901 void HAL_TSP_PVR_SPSConfig(MS_U32 u32Eng, MS_BOOL CTR_mode) in HAL_TSP_PVR_SPSConfig() argument
6903 switch(u32Eng) in HAL_TSP_PVR_SPSConfig()
6989 printf("SPS CTR mode = %p\n",&(_RegCtrl8[u32Eng].CFG8_05)); in HAL_TSP_PVR_SPSConfig()
6990 REG16_SET(&(_RegCtrl8[u32Eng].CFG8_05),CFG8_05_CTR_MODE_SPS_PVR1); //set CTR mode in HAL_TSP_PVR_SPSConfig()
6991 REG16_W(&(_RegCtrl8[u32Eng].CFG8_00_03[0]), 0x0000); //set counter IV in HAL_TSP_PVR_SPSConfig()
6992 REG16_W(&(_RegCtrl8[u32Eng].CFG8_00_03[1]), 0x0000); in HAL_TSP_PVR_SPSConfig()
6993 REG16_W(&(_RegCtrl8[u32Eng].CFG8_00_03[2]), 0x0000); in HAL_TSP_PVR_SPSConfig()
6994 REG16_W(&(_RegCtrl8[u32Eng].CFG8_00_03[3]), 0x0000); in HAL_TSP_PVR_SPSConfig()
6995 … REG16_W(&(_RegCtrl8[u32Eng].CFG8_04), CFG8_04_CTR_IV_SPS_MAX_1K); //set counter IV max vld in HAL_TSP_PVR_SPSConfig()
6996 REG16_SET(&(_RegCtrl8[u32Eng].CFG8_05),CFG8_05_LOAD_INIT_CNT_SPS1); //load counter IV in HAL_TSP_PVR_SPSConfig()