Lines Matching refs:clk_src
990 MS_U32 clk_src = REG_CLKGEN0_TS_SRC_EXT0; in HAL_TSP_TSIF_SelPad() local
1016 clk_src = REG_CLKGEN0_TS_SRC_EXT0; in HAL_TSP_TSIF_SelPad()
1020 clk_src = REG_CLKGEN0_TS_SRC_EXT1; in HAL_TSP_TSIF_SelPad()
1024 clk_src = REG_CLKGEN0_TS_SRC_EXT2; in HAL_TSP_TSIF_SelPad()
1028 clk_src = REG_CLKGEN0_TS_SRC_EXT3; in HAL_TSP_TSIF_SelPad()
1032 clk_src = REG_CLKGEN0_TS_SRC_EXT4; in HAL_TSP_TSIF_SelPad()
1036 clk_src = REG_CLKGEN0_TS_SRC_EXT5; in HAL_TSP_TSIF_SelPad()
1040 clk_src = REG_CLKGEN0_TS_SRC_EXT6; in HAL_TSP_TSIF_SelPad()
1044 clk_src = REG_CLKGEN0_TS_SRC_TSO0; in HAL_TSP_TSIF_SelPad()
1048 clk_src = REG_CLKGEN0_TS_SRC_EXT0; in HAL_TSP_TSIF_SelPad()
1055 switch(clk_src) in HAL_TSP_TSIF_SelPad()
1098 …CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) & ~REG_CLKGEN0_TS_MASK) | (clk_src<<(REG_CLKGEN0_TS0… in HAL_TSP_TSIF_SelPad()
1109 … | (clk_src<<(REG_CLKGEN0_TS1_SHIFT+REG_CLKGEN0_TS_SRC_SHIFT)); in HAL_TSP_TSIF_SelPad()
1120 … | (clk_src<<(REG_CLKGEN0_TS2_SHIFT+REG_CLKGEN0_TS_SRC_SHIFT)); in HAL_TSP_TSIF_SelPad()
1131 … | (clk_src<<(REG_CLKGEN0_TS3_SHIFT+REG_CLKGEN0_TS_SRC_SHIFT)); in HAL_TSP_TSIF_SelPad()