Lines Matching refs:TSP_Ctrl1

348     REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_STANDBY);  in HAL_TSP_HwPatch()
446         REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_PVR_CMD_QUEUE_ENABLE);  in HAL_TSP_Reset()
451         REG16_SET(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_CMDQ_RESET);  in HAL_TSP_Reset()
464         REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_CMDQ_RESET);  in HAL_TSP_Reset()
1630 …REG16_SET(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_PVR_CMD_QUEUE_ENABLE);    // for wishbone DMA (load firm…  in HAL_TSP_TSIF_FileEn()
1661                 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_PVR_CMD_QUEUE_ENABLE);  in HAL_TSP_TSIF_FileEn()
2359             REG16_SET(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_FILEIN_PAUSE);  in HAL_TSP_File_Pause()
2380             REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_FILEIN_PAUSE);  in HAL_TSP_File_Resume()
2468                 REG16_SET(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_CMDQ_RESET);  in HAL_TSP_Filein_CmdQRst()
2488                 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_CMDQ_RESET);  in HAL_TSP_Filein_CmdQRst()
2644             if (REG16_R(&_RegCtrl->TSP_Ctrl1) & TSP_CTRL1_FILEIN_PAUSE )  in HAL_TSP_Filein_GetState()