Lines Matching refs:PVR2_Config
357 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_RLD); in HAL_TSP_HwPatch()
955 REG32_SET(&_RegCtrl->PVR2_Config, TSP_TS_IF2_EN); in HAL_TSP_TSIF_LiveEn()
975 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_TS_IF2_EN); in HAL_TSP_TSIF_LiveEn()
1704 REG32_SET(&_RegCtrl->PVR2_Config, TSP_TS_DATA2_SWAP); in HAL_TSP_TSIF_BitSwap()
1724 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_TS_DATA2_SWAP); in HAL_TSP_TSIF_BitSwap()
1750 REG32_SET(&_RegCtrl->PVR2_Config, TSP_EXT_SYNC_SEL2); in HAL_TSP_TSIF_ExtSync()
1772 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_EXT_SYNC_SEL2); in HAL_TSP_TSIF_ExtSync()
1844 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_P_SEL2); in HAL_TSP_TSIF_Parl()
1864 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_P_SEL2); in HAL_TSP_TSIF_Parl()
4176 REG32_SET(&_RegCtrl->PVR2_Config, TSP_V_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4179 REG32_SET(&_RegCtrl->PVR2_Config, TSP_V3d_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4182 REG32_SET(&_RegCtrl->PVR2_Config, TSP_A_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4185 REG32_SET(&_RegCtrl->PVR2_Config, TSP_AD_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4188 REG32_SET(&_RegCtrl->PVR2_Config, TSP_AC_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4191 REG32_SET(&_RegCtrl->PVR2_Config, TSP_ADD_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4202 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_V_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4205 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_V3d_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4208 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_A_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4211 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_AD_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4214 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_AC_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4217 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_ADD_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4640 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_REG_PINGPONG_EN); in HAL_PVR_Init()
4674 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_REG_PINGPONG_EN); in HAL_PVR_Exit()
4679 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR); in HAL_PVR_Exit()
4680 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR); in HAL_PVR_Exit()
4728 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR); in HAL_PVR_Start()
4729 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR); in HAL_PVR_Start()
4732 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_EN); in HAL_PVR_Start()
4771 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_EN); in HAL_PVR_Stop()
4796 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_PAUSE); in HAL_PVR_Pause()
4816 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_PAUSE); in HAL_PVR_Pause()
5413 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_PKT192_EN); in HAL_PVR_SetStrPacketMode()
5433 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_PKT192_EN); in HAL_PVR_SetStrPacketMode()
5461 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_RLD); in HAL_PVR_GetPVRTimeStamp()
5465 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_RLD); in HAL_PVR_GetPVRTimeStamp()
5499 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_WLD); in HAL_PVR_SetPVRTimeStamp()
5503 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_WLD); in HAL_PVR_SetPVRTimeStamp()
5571 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_PVR_ALIGN_EN); in HAL_PVR_Alignment_Enable()
5591 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_PVR_ALIGN_EN); in HAL_PVR_Alignment_Enable()
5682 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR1_BLOCK_DIS); in HAL_PVR_Block_Dis()
5685 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_BLOCK_DIS); in HAL_PVR_Block_Dis()
5702 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR1_BLOCK_DIS); in HAL_PVR_Block_Dis()
5705 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_BLOCK_DIS); in HAL_PVR_Block_Dis()
5728 …REG32_MSK_W(&_RegCtrl->PVR2_Config, TSP_PVR2_BURST_LEN_MASK, (u16BurstMode << TSP_PVR2_BURST_LEN_S… in HAL_PVR_BurstLen()
6457 REG32_SET(&_RegCtrl->PVR2_Config, TSP_TEI_SKIP_PKT2); in HAL_TSP_TEI_SKIP()
6477 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_TEI_SKIP_PKT2); in HAL_TSP_TEI_SKIP()