Lines Matching refs:CFG_23
353 REG16_SET(&_RegCtrl2->CFG_23, CFG_23_PID_BYPASS4_REC); in HAL_TSP_HwPatch()
359 REG16_SET((&_RegCtrl2->CFG_23), CFG_23_PVR4_LPCR1_RLD); in HAL_TSP_HwPatch()
4652 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_PVR4_REG_PINGPONG_EN); in HAL_PVR_Init()
4694 REG16_CLR(&(_RegCtrl2->CFG_23), CFG_23_PVR4_REG_PINGPONG_EN); in HAL_PVR_Exit()
4697 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_RST_WADR); in HAL_PVR_Exit()
4698 REG16_CLR(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_RST_WADR); in HAL_PVR_Exit()
4744 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_RST_WADR); in HAL_PVR_Start()
4745 REG16_CLR(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_RST_WADR); in HAL_PVR_Start()
4748 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_EN); in HAL_PVR_Start()
4779 REG16_CLR(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_EN); in HAL_PVR_Stop()
4802 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_PAUSE); in HAL_PVR_Pause()
4822 REG16_CLR(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_PAUSE); in HAL_PVR_Pause()
4849 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_PID_BYPASS4_REC); in HAL_PVR_RecPid()
4850 REG16_CLR(&(_RegCtrl2->CFG_23), CFG_23_REC_ALL4); in HAL_PVR_RecPid()
4873 REG16_CLR(&(_RegCtrl2->CFG_23), CFG_23_PID_BYPASS4_REC); in HAL_PVR_RecPid()
4874 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_REC_ALL4); in HAL_PVR_RecPid()
5419 REG16_SET((&_RegCtrl2->CFG_23), CFG_23_PVR4_PKT192_EN); in HAL_PVR_SetStrPacketMode()
5439 REG16_CLR((&_RegCtrl2->CFG_23), CFG_23_PVR4_PKT192_EN); in HAL_PVR_SetStrPacketMode()
5475 REG16_CLR((&_RegCtrl2->CFG_23), CFG_23_PVR4_LPCR1_RLD); in HAL_PVR_GetPVRTimeStamp()
5479 REG16_SET((&_RegCtrl2->CFG_23), CFG_23_PVR4_LPCR1_RLD); in HAL_PVR_GetPVRTimeStamp()
5513 REG16_SET(&_RegCtrl2->CFG_23, CFG_23_PVR4_LPCR1_WLD); in HAL_PVR_SetPVRTimeStamp()
5517 REG16_CLR(&_RegCtrl2->CFG_23, CFG_23_PVR4_LPCR1_WLD); in HAL_PVR_SetPVRTimeStamp()
5577 REG16_SET(&_RegCtrl2->CFG_23, CFG_23_PVR4_PVR_ALIGN_EN); in HAL_PVR_Alignment_Enable()
5597 REG16_CLR(&_RegCtrl2->CFG_23, CFG_23_PVR4_PVR_ALIGN_EN); in HAL_PVR_Alignment_Enable()
5691 REG16_SET(&_RegCtrl2->CFG_23, CFG_23_PVR4_BLOCK_DIS); in HAL_PVR_Block_Dis()
5711 REG16_CLR(&_RegCtrl2->CFG_23, CFG_23_PVR4_BLOCK_DIS); in HAL_PVR_Block_Dis()
5734 …REG16_MSK_W(&_RegCtrl2->CFG_23, CFG_23_PVR4_BURST_LEN_MASK, (u16BurstMode << CFG_23_PVR4_BURST_LEN… in HAL_PVR_BurstLen()