Lines Matching refs:_REGFIQ
95 REG_FIQ* _REGFIQ = NULL; variable
141 _REGFIQ = (REG_FIQ*)(_u32RegBase + FQ_REG_CTRL_BASE); in HAL_FQ_SetBank()
153 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_head), MIU_FQ(phyMiuOffsetFQBuf) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
154 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_tail), MIU_FQ(u32EndAddr) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
155 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_mid), MIU_FQ(phyMiuOffsetFQBuf) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
160 FQ32_W(&(_REGFIQ[u32FQEng].rush_addr), MIU_FQ(u32RushAddr) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetRushAddr()
166 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config… in HAL_FQ_PVR_Start()
167 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config… in HAL_FQ_PVR_Start()
170 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config… in HAL_FQ_PVR_Start()
175 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config… in HAL_FQ_PVR_Stop()
182 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fig_config3), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fig_config… in HAL_FQ_Read_Enable()
186 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fig_config3), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fig_config… in HAL_FQ_Read_Enable()
196 Reg = &_REGFIQ[u32FQEng].Reg_fiq_config1; in HAL_FQ_BurstLen()
201 Reg = &_REGFIQ[u32FQEng].Reg_fiq_config0; in HAL_FQ_BurstLen()
208 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config… in HAL_FQ_Rush_Enable()
209 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config… in HAL_FQ_Rush_Enable()
216 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config1), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config… in HAL_FQ_Bypass()
220 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config1), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config… in HAL_FQ_Bypass()
228 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config1), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config… in HAL_FQ_BypassFilein()
232 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config1), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config… in HAL_FQ_BypassFilein()
240 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config… in HAL_FQ_SWReset()
244 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config… in HAL_FQ_SWReset()
252 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config… in HAL_FQ_AddrMode()
256 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config… in HAL_FQ_AddrMode()
262 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config… in HAL_FQ_GetRead()
263 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config… in HAL_FQ_GetRead()
265 return (_HAL_REG32_R(&(_REGFIQ[u32FQEng].Fiq2mi2_radr_r)) << MIU_BUS); in HAL_FQ_GetRead()
270 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config… in HAL_FQ_GetWrite()
271 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config… in HAL_FQ_GetWrite()
273 return (_HAL_REG32_R(&(_REGFIQ[u32FQEng].str2mi2_wadr_r)) << MIU_BUS); in HAL_FQ_GetWrite()
290 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_int), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_int)), u… in HAL_FQ_INT_Enable()
295 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_int), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_int)), u16… in HAL_FQ_INT_Disable()
300 return _HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_int)) & FIQ_CFG10_INT_STATUS_MASK; in HAL_FQ_INT_GetHW()
305 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_int), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_int)), u16… in HAL_FQ_INT_ClrHW()
306 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_int), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_int)), u16… in HAL_FQ_INT_ClrHW()
313 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fig_config2), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fig_config… in HAL_FQ_Timestamp_Sel()
317 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fig_config2), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fig_config… in HAL_FQ_Timestamp_Sel()
325 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config1), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config… in HAL_FQ_GetPVRTimeStamp()
326 u32Timestamp = _HAL_REG32_R(&(_REGFIQ[u32FQEng].lpcr1)); in HAL_FQ_GetPVRTimeStamp()
327 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config1), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config… in HAL_FQ_GetPVRTimeStamp()
334 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config1), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config… in HAL_FQ_SetPVRTimeStamp()
335 FQ32_W(&(_REGFIQ[u32FQEng].lpcr1), u32Stamp); in HAL_FQ_SetPVRTimeStamp()
336 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config1), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config… in HAL_FQ_SetPVRTimeStamp()
355 …FQ16_W(&_REGFIQ[u32FQEng].Reg_fig_config3, _CLR_(_HAL_REG16_R(&_REGFIQ[u32FQEng].Reg_fig_config3),… in HAL_FQ_BypassSrcFlt()
359 …FQ16_W(&_REGFIQ[u32FQEng].Reg_fig_config3, _SET_(_HAL_REG16_R(&_REGFIQ[u32FQEng].Reg_fig_config3),… in HAL_FQ_BypassSrcFlt()
365 REG16_FQ *Reg = &_REGFIQ[u32FQEng].Fiq_Src_Filter[u32SrcFltId >> 1]; in HAL_FQ_SrcFlt_SetSyncByte()
383 …FQ16_W(&_REGFIQ[u32FQEng].REG_FIQ_28, _SET_(_HAL_REG16_R(&_REGFIQ[u32FQEng].REG_FIQ_28), (FIQ_CFG2… in HAL_FQ_SrcFlt_Enable()
387 …FQ16_W(&_REGFIQ[u32FQEng].REG_FIQ_28, _CLR_(_HAL_REG16_R(&_REGFIQ[u32FQEng].REG_FIQ_28), (FIQ_CFG2… in HAL_FQ_SrcFlt_Enable()
393 REG16_FQ *Reg = &_REGFIQ[u32FQEng].Fiq_Filter[u32FltId]; in HAL_FQ_Flt_SetPid()
407 REG16_FQ *Reg = &_REGFIQ[u32FQEng].Fiq_Filter_SyncByte[u32FltId >> 1]; in HAL_FQ_Flt_SetSyncByte()
423 REG16_FQ *Reg = &_REGFIQ[u32FQEng].Fiq_Filter[u32FltId]; in HAL_FQ_Flt_Enable()
437 REG16_FQ *Reg = &_REGFIQ[u32FQMuxEng + FQ_MUX_START_ID].Reg_fiq_config1; in HAL_FQ_MUX_Src()
451 REG16_FQ *Reg = &_REGFIQ[u32FQMuxEng + FQ_MUX_START_ID].Reg_fig_config3; in HAL_FQ_MUX_RushModeEnable()