167 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config…  in HAL_FQ_PVR_Start()
175 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config…  in HAL_FQ_PVR_Stop()
186 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fig_config3), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fig_config…  in HAL_FQ_Read_Enable()
197 …FQ16_W(Reg, _CLR_(_HAL_REG16_R(Reg), FIG_CFGB_READ_BURST_LEN_MASK) | (u16BurstLen << FIG_CFGB_READ…  in HAL_FQ_BurstLen()
202 …FQ16_W(Reg, _CLR_(_HAL_REG16_R(Reg), FIQ_CFG0_BURST_LEN_MASK) | (u16BurstLen << FIQ_CFG0_BURST_LEN…  in HAL_FQ_BurstLen()
209 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config…  in HAL_FQ_Rush_Enable()
220 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config1), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config…  in HAL_FQ_Bypass()
232 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config1), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config…  in HAL_FQ_BypassFilein()
240 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config…  in HAL_FQ_SWReset()
256 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config…  in HAL_FQ_AddrMode()
263 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config…  in HAL_FQ_GetRead()
271 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config…  in HAL_FQ_GetWrite()
295 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_int), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_int)), u16…  in HAL_FQ_INT_Disable()
306 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_int), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_int)), u16…  in HAL_FQ_INT_ClrHW()
317 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fig_config2), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fig_config…  in HAL_FQ_Timestamp_Sel()
327 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config1), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config…  in HAL_FQ_GetPVRTimeStamp()
336 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config1), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config…  in HAL_FQ_SetPVRTimeStamp()
355 …FQ16_W(&_REGFIQ[u32FQEng].Reg_fig_config3, _CLR_(_HAL_REG16_R(&_REGFIQ[u32FQEng].Reg_fig_config3),…  in HAL_FQ_BypassSrcFlt()
371         FQ16_W(Reg, _CLR_(_HAL_REG16_R(Reg), u16Mask) | (*pu8SyncByte << u16Shift));  in HAL_FQ_SrcFlt_SetSyncByte()
387 …FQ16_W(&_REGFIQ[u32FQEng].REG_FIQ_28, _CLR_(_HAL_REG16_R(&_REGFIQ[u32FQEng].REG_FIQ_28), (FIQ_CFG2…  in HAL_FQ_SrcFlt_Enable()
397 …   FQ16_W(Reg, _CLR_(_HAL_REG16_R(Reg), FIQ_FILTER_PID_MASK) | (*pu16Pid << FIQ_FILTER_PID_SHIFT));  in HAL_FQ_Flt_SetPid()
413         FQ16_W(Reg, _CLR_(_HAL_REG16_R(Reg), u16Mask) | (*pu8SyncByte << u16Shift));  in HAL_FQ_Flt_SetSyncByte()
431         FQ16_W(Reg, _CLR_(_HAL_REG16_R(Reg), FIQ_FILTER_EN));  in HAL_FQ_Flt_Enable()
441 …FQ16_W(Reg, _CLR_(_HAL_REG16_R(Reg), FIG_CFGB_REG_FIQ_MUX_SRC_MASK) | (*pu16Path << FIG_CFGB_REG_F…  in HAL_FQ_MUX_Src()
459         FQ16_W(Reg, _CLR_(_HAL_REG16_R(Reg), FIQ_CFGF_RUSH_MODE_EN));  in HAL_FQ_MUX_RushModeEnable()