192     REG16_FQ    *Reg = NULL;  in HAL_FQ_BurstLen()  local
196         Reg = &_REGFIQ[u32FQEng].Reg_fiq_config1;  in HAL_FQ_BurstLen()
197 …FQ16_W(Reg, _CLR_(_HAL_REG16_R(Reg), FIG_CFGB_READ_BURST_LEN_MASK) | (u16BurstLen << FIG_CFGB_READ…  in HAL_FQ_BurstLen()
201         Reg = &_REGFIQ[u32FQEng].Reg_fiq_config0;  in HAL_FQ_BurstLen()
202 …FQ16_W(Reg, _CLR_(_HAL_REG16_R(Reg), FIQ_CFG0_BURST_LEN_MASK) | (u16BurstLen << FIQ_CFG0_BURST_LEN…  in HAL_FQ_BurstLen()
365     REG16_FQ    *Reg = &_REGFIQ[u32FQEng].Fiq_Src_Filter[u32SrcFltId >> 1];  in HAL_FQ_SrcFlt_SetSyncByte()  local
371         FQ16_W(Reg, _CLR_(_HAL_REG16_R(Reg), u16Mask) | (*pu8SyncByte << u16Shift));  in HAL_FQ_SrcFlt_SetSyncByte()
375         *pu8SyncByte = (MS_U8)((_HAL_REG16_R(Reg) & u16Mask) >> u16Shift);  in HAL_FQ_SrcFlt_SetSyncByte()
393     REG16_FQ    *Reg = &_REGFIQ[u32FQEng].Fiq_Filter[u32FltId];  in HAL_FQ_Flt_SetPid()  local
397 …   FQ16_W(Reg, _CLR_(_HAL_REG16_R(Reg), FIQ_FILTER_PID_MASK) | (*pu16Pid << FIQ_FILTER_PID_SHIFT));  in HAL_FQ_Flt_SetPid()
401         *pu16Pid = (MS_U16)((_HAL_REG16_R(Reg) & FIQ_FILTER_PID_MASK) >> FIQ_FILTER_PID_SHIFT);  in HAL_FQ_Flt_SetPid()
407     REG16_FQ    *Reg = &_REGFIQ[u32FQEng].Fiq_Filter_SyncByte[u32FltId >> 1];  in HAL_FQ_Flt_SetSyncByte()  local
413         FQ16_W(Reg, _CLR_(_HAL_REG16_R(Reg), u16Mask) | (*pu8SyncByte << u16Shift));  in HAL_FQ_Flt_SetSyncByte()
417         *pu8SyncByte = (MS_U8)((_HAL_REG16_R(Reg) & u16Mask) >> u16Shift);  in HAL_FQ_Flt_SetSyncByte()
423     REG16_FQ    *Reg = &_REGFIQ[u32FQEng].Fiq_Filter[u32FltId];  in HAL_FQ_Flt_Enable()  local
427         FQ16_W(Reg, _SET_(_HAL_REG16_R(Reg), FIQ_FILTER_EN));  in HAL_FQ_Flt_Enable()
431         FQ16_W(Reg, _CLR_(_HAL_REG16_R(Reg), FIQ_FILTER_EN));  in HAL_FQ_Flt_Enable()
437     REG16_FQ    *Reg = &_REGFIQ[u32FQMuxEng + FQ_MUX_START_ID].Reg_fiq_config1;  in HAL_FQ_MUX_Src()  local
441 …FQ16_W(Reg, _CLR_(_HAL_REG16_R(Reg), FIG_CFGB_REG_FIQ_MUX_SRC_MASK) | (*pu16Path << FIG_CFGB_REG_F…  in HAL_FQ_MUX_Src()
445 …*pu16Path = (MS_U16)((_HAL_REG16_R(Reg) & FIG_CFGB_REG_FIQ_MUX_SRC_MASK) >> FIG_CFGB_REG_FIQ_MUX_S…  in HAL_FQ_MUX_Src()
451     REG16_FQ    *Reg = &_REGFIQ[u32FQMuxEng + FQ_MUX_START_ID].Reg_fig_config3;  in HAL_FQ_MUX_RushModeEnable()  local
455         FQ16_W(Reg, _SET_(_HAL_REG16_R(Reg), FIQ_CFGF_RUSH_MODE_EN));  in HAL_FQ_MUX_RushModeEnable()
459         FQ16_W(Reg, _CLR_(_HAL_REG16_R(Reg), FIQ_CFGF_RUSH_MODE_EN));  in HAL_FQ_MUX_RushModeEnable()