Lines Matching refs:FQ16_W
101 #define FQ16_W(reg, value); {(reg)->data = ((value) & 0x0000FFFF);} macro
166 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config… in HAL_FQ_PVR_Start()
167 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config… in HAL_FQ_PVR_Start()
170 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config… in HAL_FQ_PVR_Start()
175 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config… in HAL_FQ_PVR_Stop()
182 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fig_config3), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fig_config… in HAL_FQ_Read_Enable()
186 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fig_config3), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fig_config… in HAL_FQ_Read_Enable()
197 …FQ16_W(Reg, _CLR_(_HAL_REG16_R(Reg), FIG_CFGB_READ_BURST_LEN_MASK) | (u16BurstLen << FIG_CFGB_READ… in HAL_FQ_BurstLen()
202 …FQ16_W(Reg, _CLR_(_HAL_REG16_R(Reg), FIQ_CFG0_BURST_LEN_MASK) | (u16BurstLen << FIQ_CFG0_BURST_LEN… in HAL_FQ_BurstLen()
208 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config… in HAL_FQ_Rush_Enable()
209 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config… in HAL_FQ_Rush_Enable()
216 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config1), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config… in HAL_FQ_Bypass()
220 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config1), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config… in HAL_FQ_Bypass()
228 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config1), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config… in HAL_FQ_BypassFilein()
232 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config1), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config… in HAL_FQ_BypassFilein()
240 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config… in HAL_FQ_SWReset()
244 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config… in HAL_FQ_SWReset()
252 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config… in HAL_FQ_AddrMode()
256 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config… in HAL_FQ_AddrMode()
262 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config… in HAL_FQ_GetRead()
263 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config… in HAL_FQ_GetRead()
270 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config… in HAL_FQ_GetWrite()
271 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config0), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config… in HAL_FQ_GetWrite()
290 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_int), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_int)), u… in HAL_FQ_INT_Enable()
295 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_int), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_int)), u16… in HAL_FQ_INT_Disable()
305 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_int), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_int)), u16… in HAL_FQ_INT_ClrHW()
306 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_int), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_int)), u16… in HAL_FQ_INT_ClrHW()
313 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fig_config2), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fig_config… in HAL_FQ_Timestamp_Sel()
317 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fig_config2), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fig_config… in HAL_FQ_Timestamp_Sel()
325 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config1), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config… in HAL_FQ_GetPVRTimeStamp()
327 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config1), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config… in HAL_FQ_GetPVRTimeStamp()
334 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config1), _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config… in HAL_FQ_SetPVRTimeStamp()
336 …FQ16_W(&(_REGFIQ[u32FQEng].Reg_fiq_config1), _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config… in HAL_FQ_SetPVRTimeStamp()
355 …FQ16_W(&_REGFIQ[u32FQEng].Reg_fig_config3, _CLR_(_HAL_REG16_R(&_REGFIQ[u32FQEng].Reg_fig_config3),… in HAL_FQ_BypassSrcFlt()
359 …FQ16_W(&_REGFIQ[u32FQEng].Reg_fig_config3, _SET_(_HAL_REG16_R(&_REGFIQ[u32FQEng].Reg_fig_config3),… in HAL_FQ_BypassSrcFlt()
371 FQ16_W(Reg, _CLR_(_HAL_REG16_R(Reg), u16Mask) | (*pu8SyncByte << u16Shift)); in HAL_FQ_SrcFlt_SetSyncByte()
383 …FQ16_W(&_REGFIQ[u32FQEng].REG_FIQ_28, _SET_(_HAL_REG16_R(&_REGFIQ[u32FQEng].REG_FIQ_28), (FIQ_CFG2… in HAL_FQ_SrcFlt_Enable()
387 …FQ16_W(&_REGFIQ[u32FQEng].REG_FIQ_28, _CLR_(_HAL_REG16_R(&_REGFIQ[u32FQEng].REG_FIQ_28), (FIQ_CFG2… in HAL_FQ_SrcFlt_Enable()
397 … FQ16_W(Reg, _CLR_(_HAL_REG16_R(Reg), FIQ_FILTER_PID_MASK) | (*pu16Pid << FIQ_FILTER_PID_SHIFT)); in HAL_FQ_Flt_SetPid()
413 FQ16_W(Reg, _CLR_(_HAL_REG16_R(Reg), u16Mask) | (*pu8SyncByte << u16Shift)); in HAL_FQ_Flt_SetSyncByte()
427 FQ16_W(Reg, _SET_(_HAL_REG16_R(Reg), FIQ_FILTER_EN)); in HAL_FQ_Flt_Enable()
431 FQ16_W(Reg, _CLR_(_HAL_REG16_R(Reg), FIQ_FILTER_EN)); in HAL_FQ_Flt_Enable()
441 …FQ16_W(Reg, _CLR_(_HAL_REG16_R(Reg), FIG_CFGB_REG_FIQ_MUX_SRC_MASK) | (*pu16Path << FIG_CFGB_REG_F… in HAL_FQ_MUX_Src()
455 FQ16_W(Reg, _SET_(_HAL_REG16_R(Reg), FIQ_CFGF_RUSH_MODE_EN)); in HAL_FQ_MUX_RushModeEnable()
459 FQ16_W(Reg, _CLR_(_HAL_REG16_R(Reg), FIQ_CFGF_RUSH_MODE_EN)); in HAL_FQ_MUX_RushModeEnable()