Lines Matching refs:clk_src
914 MS_U32 clk_src = REG_CLKGEN0_TS_SRC_EXT0; in HAL_TSP_TSIF_SelPad() local
943 clk_src = REG_CLKGEN0_TS_SRC_EXT0; in HAL_TSP_TSIF_SelPad()
947 clk_src = REG_CLKGEN0_TS_SRC_EXT1; in HAL_TSP_TSIF_SelPad()
951 clk_src = REG_CLKGEN0_TS_SRC_EXT2; in HAL_TSP_TSIF_SelPad()
955 clk_src = REG_CLKGEN0_TS_SRC_EXT3; in HAL_TSP_TSIF_SelPad()
959 clk_src = REG_CLKGEN0_TS_SRC_EXT4; in HAL_TSP_TSIF_SelPad()
963 clk_src = REG_CLKGEN0_TS_SRC_EXT5; in HAL_TSP_TSIF_SelPad()
967 clk_src = REG_CLKGEN0_TS_SRC_EXT6; in HAL_TSP_TSIF_SelPad()
971 clk_src = REG_CLKGEN0_TS_SRC_TSO0; in HAL_TSP_TSIF_SelPad()
975 clk_src = REG_CLKGEN0_TS_SRC_TSIO0; in HAL_TSP_TSIF_SelPad()
979 clk_src = REG_CLKGEN0_TS_SRC_DMD0; in HAL_TSP_TSIF_SelPad()
983 clk_src = REG_CLKGEN0_TS_SRC_DMD1; in HAL_TSP_TSIF_SelPad()
989 switch(clk_src) in HAL_TSP_TSIF_SelPad()
1040 …CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) & ~REG_CLKGEN0_TS_MASK) | (clk_src<<(REG_CLKGEN0_TS0… in HAL_TSP_TSIF_SelPad()
1050 …REG_CLKGEN0_TS1_CLK) & ~(REG_CLKGEN0_TS_MASK<<REG_CLKGEN0_TS1_SHIFT)) | (clk_src<<(REG_CLKGEN0_TS1… in HAL_TSP_TSIF_SelPad()
1059 …REG_CLKGEN0_TS2_CLK) & ~(REG_CLKGEN0_TS_MASK<<REG_CLKGEN0_TS2_SHIFT)) | (clk_src<<(REG_CLKGEN0_TS2… in HAL_TSP_TSIF_SelPad()
1068 …REG_CLKGEN0_TS3_CLK) & ~(REG_CLKGEN0_TS_MASK<<REG_CLKGEN0_TS3_SHIFT)) | (clk_src<<(REG_CLKGEN0_TS3… in HAL_TSP_TSIF_SelPad()