Lines Matching refs:_RegCtrl2
46 static REG_Ctrl2* _RegCtrl2 = NULL; // TSP3 variable
189 _RegCtrl2 = (REG_Ctrl2*)(u32BankAddr + 0xE0400UL); // TSP3 0x1702, in HAL_TSP_SetBank()
273 REG16_SET(&_RegCtrl2->CFG_16, CFG_16_PID_BYPASS3_REC); in HAL_TSP_HwPatch()
274 REG16_SET(&_RegCtrl2->CFG_23, CFG_23_PID_BYPASS4_REC); in HAL_TSP_HwPatch()
279 REG16_SET((&_RegCtrl2->CFG_16), CFG_16_PVR3_LPCR1_RLD); in HAL_TSP_HwPatch()
280 REG16_SET((&_RegCtrl2->CFG_23), CFG_23_PVR4_LPCR1_RLD); in HAL_TSP_HwPatch()
371 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1); in HAL_TSP_Reset()
376 REG16_SET(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1); in HAL_TSP_Reset()
377 REG16_SET(&_RegCtrl2->CFG_05, CFG_05_RST_CMDQ_FILEIN_TSIF2); in HAL_TSP_Reset()
378 REG16_SET(&_RegCtrl2->CFG_0A, CFG_0A_RST_CMDQ_FILEIN_TSIF3); in HAL_TSP_Reset()
389 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1); in HAL_TSP_Reset()
390 REG16_CLR(&_RegCtrl2->CFG_05, CFG_05_RST_CMDQ_FILEIN_TSIF2); in HAL_TSP_Reset()
391 REG16_CLR(&_RegCtrl2->CFG_0A, CFG_0A_RST_CMDQ_FILEIN_TSIF3); in HAL_TSP_Reset()
403 REG16_SET(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT0); in HAL_TSP_Path_Reset()
404 REG16_SET(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF0 | CFG_12_REG_REST_PDBF0); in HAL_TSP_Path_Reset()
408 REG16_CLR(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF0 | CFG_12_REG_REST_PDBF0); in HAL_TSP_Path_Reset()
409 REG16_CLR(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT0); in HAL_TSP_Path_Reset()
415 REG16_SET(&_RegCtrl2->CFG_00,CFG_00_RST_TS_FIN1); in HAL_TSP_Path_Reset()
416 REG16_SET(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT1); in HAL_TSP_Path_Reset()
417 REG16_SET(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF1 | CFG_12_REG_REST_PDBF1); in HAL_TSP_Path_Reset()
421 REG16_CLR(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF1 | CFG_12_REG_REST_PDBF1); in HAL_TSP_Path_Reset()
422 REG16_CLR(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT1); in HAL_TSP_Path_Reset()
423 REG16_CLR(&_RegCtrl2->CFG_00,CFG_00_RST_TS_FIN1); in HAL_TSP_Path_Reset()
428 REG16_SET(&_RegCtrl2->CFG_05,CFG_05_RST_TS_FIN2); in HAL_TSP_Path_Reset()
429 REG16_SET(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT2); in HAL_TSP_Path_Reset()
430 REG16_SET(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF2 | CFG_12_REG_REST_PDBF2); in HAL_TSP_Path_Reset()
434 REG16_CLR(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF2 | CFG_12_REG_REST_PDBF2); in HAL_TSP_Path_Reset()
435 REG16_CLR(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT2); in HAL_TSP_Path_Reset()
436 REG16_CLR(&_RegCtrl2->CFG_05,CFG_05_RST_TS_FIN2); in HAL_TSP_Path_Reset()
441 REG16_SET(&_RegCtrl2->CFG_0A,CFG_0A_RST_TS_FIN3); in HAL_TSP_Path_Reset()
442 REG16_SET(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT3); in HAL_TSP_Path_Reset()
443 REG16_SET(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF3 | CFG_12_REG_REST_PDBF3); in HAL_TSP_Path_Reset()
447 REG16_CLR(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF3 | CFG_12_REG_REST_PDBF3); in HAL_TSP_Path_Reset()
448 REG16_CLR(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT3); in HAL_TSP_Path_Reset()
449 REG16_CLR(&_RegCtrl2->CFG_0A,CFG_0A_RST_TS_FIN3); in HAL_TSP_Path_Reset()
761 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF0); in HAL_TSP_PktBuf_Reset()
764 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF1); in HAL_TSP_PktBuf_Reset()
767 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF2); in HAL_TSP_PktBuf_Reset()
770 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF3); in HAL_TSP_PktBuf_Reset()
781 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF0); in HAL_TSP_PktBuf_Reset()
784 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF1); in HAL_TSP_PktBuf_Reset()
787 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF2); in HAL_TSP_PktBuf_Reset()
790 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF3); in HAL_TSP_PktBuf_Reset()
805 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF0); in HAL_TSP_RecvBuf_Reset()
808 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF1); in HAL_TSP_RecvBuf_Reset()
811 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF2); in HAL_TSP_RecvBuf_Reset()
814 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF3); in HAL_TSP_RecvBuf_Reset()
825 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF0); in HAL_TSP_RecvBuf_Reset()
828 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF1); in HAL_TSP_RecvBuf_Reset()
831 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF2); in HAL_TSP_RecvBuf_Reset()
834 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF3); in HAL_TSP_RecvBuf_Reset()
882 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_TS_IF3_EN); in HAL_TSP_TSIF_LiveEn()
902 REG16_CLR(&_RegCtrl2->CFG_0B, CFG_0B_TS_IF3_EN); in HAL_TSP_TSIF_LiveEn()
1569 …REG16_SET(&_RegCtrl2->CFG_01, CFG_01_TSP_FILE_SEGMENT1); // for wishbone DMA (load firm… in HAL_TSP_TSIF_FileEn()
1570 REG16_SET(&_RegCtrl2->CFG_00, CFG_00_TSP_FILE_SEGMENT_TSIF1); in HAL_TSP_TSIF_FileEn()
1571 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_TS_DATA_PORT_SEL1); in HAL_TSP_TSIF_FileEn()
1572 REG16_SET(&_RegCtrl2->CFG_00, CFG_00_TSP_FILE_IN_TSIF1_EN); //filein enable in HAL_TSP_TSIF_FileEn()
1575 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_TSP_FILE_SEGMENT2); in HAL_TSP_TSIF_FileEn()
1576 REG16_SET(&_RegCtrl2->CFG_05, CFG_05_TSP_FILE_SEGMENT_TSIF2); in HAL_TSP_TSIF_FileEn()
1577 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_TS_DATA_PORT_SEL2); in HAL_TSP_TSIF_FileEn()
1578 REG16_SET(&_RegCtrl2->CFG_05, CFG_05_TSP_FILEIN_TSIF2); in HAL_TSP_TSIF_FileEn()
1581 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_TSP_FILE_SEGMENT3); in HAL_TSP_TSIF_FileEn()
1582 REG16_SET(&_RegCtrl2->CFG_0A, CFG_0A_TSP_FILE_SEGMENT_TSIF3); in HAL_TSP_TSIF_FileEn()
1583 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_TS_DATA_PORT_SEL3); in HAL_TSP_TSIF_FileEn()
1584 REG16_SET(&_RegCtrl2->CFG_0A, CFG_0A_TSP_FILE_IN_TSIF3); in HAL_TSP_TSIF_FileEn()
1600 REG16_CLR(&_RegCtrl2->CFG_01, CFG_01_TSP_FILE_SEGMENT1); in HAL_TSP_TSIF_FileEn()
1601 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_TSP_FILE_SEGMENT_TSIF1); in HAL_TSP_TSIF_FileEn()
1602 REG16_CLR(&_RegCtrl2->CFG_01, CFG_01_TS_DATA_PORT_SEL1); in HAL_TSP_TSIF_FileEn()
1603 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_TSP_FILE_IN_TSIF1_EN); in HAL_TSP_TSIF_FileEn()
1606 REG16_CLR(&_RegCtrl2->CFG_06, CFG_06_TSP_FILE_SEGMENT2); in HAL_TSP_TSIF_FileEn()
1607 REG16_CLR(&_RegCtrl2->CFG_05, CFG_05_TSP_FILE_SEGMENT_TSIF2); in HAL_TSP_TSIF_FileEn()
1608 REG16_CLR(&_RegCtrl2->CFG_05, CFG_05_TSP_FILEIN_TSIF2); in HAL_TSP_TSIF_FileEn()
1609 REG16_CLR(&_RegCtrl2->CFG_06, CFG_06_TS_DATA_PORT_SEL2); in HAL_TSP_TSIF_FileEn()
1612 REG16_CLR(&_RegCtrl2->CFG_0B, CFG_0B_TSP_FILE_SEGMENT3); in HAL_TSP_TSIF_FileEn()
1613 REG16_CLR(&_RegCtrl2->CFG_0A, CFG_0A_TSP_FILE_SEGMENT_TSIF3); in HAL_TSP_TSIF_FileEn()
1614 REG16_CLR(&_RegCtrl2->CFG_0B, CFG_0B_TS_DATA_PORT_SEL3); in HAL_TSP_TSIF_FileEn()
1615 REG16_CLR(&_RegCtrl2->CFG_0A, CFG_0A_TSP_FILE_IN_TSIF3); in HAL_TSP_TSIF_FileEn()
1641 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_TS_DATA3_SWAP); in HAL_TSP_TSIF_BitSwap()
1661 REG16_CLR(&_RegCtrl2->CFG_0B, CFG_0B_TS_DATA3_SWAP); in HAL_TSP_TSIF_BitSwap()
1687 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_EXT_SYNC_SEL3); in HAL_TSP_TSIF_ExtSync()
1709 REG16_CLR(&_RegCtrl2->CFG_0B, CFG_0B_EXT_SYNC_SEL3); in HAL_TSP_TSIF_ExtSync()
1829 REG16_SET(&(_RegCtrl2->CFG_0B), CFG_0B_P_SEL3); in HAL_TSP_TSIF_Parl()
1849 REG16_CLR(&(_RegCtrl2->CFG_0B), CFG_0B_P_SEL3); in HAL_TSP_TSIF_Parl()
1975 REG16_MSK_W(&_RegCtrl2->CFG_01, CFG_01_PDFLT2_FILE_SRC, u16Src); in HAL_TSP_ReDirect_File()
2332 …REG16_W(&_RegCtrl2->CFG_02, (REG16_R(&_RegCtrl2->CFG_02) & ~CFG_02_PKT_CHK_SIZE_FIN1) | (CFG_02_PK… in HAL_TSP_Filein_PktSize()
2335 …REG16_W(&_RegCtrl2->CFG_07, (REG16_R(&_RegCtrl2->CFG_07) & ~CFG_07_PKT_CHK_SIZE_FIN2) | (CFG_07_PK… in HAL_TSP_Filein_PktSize()
2338 …REG16_W(&_RegCtrl2->CFG_0C, (REG16_R(&_RegCtrl2->CFG_0C) & ~CFG_0C_PKT_CHK_SIZE_FIN3) | (CFG_0C_PK… in HAL_TSP_Filein_PktSize()
2360 REG32_W(&_RegCtrl2->CFG_30_31, phyMiuOffsetFileinAddr); in HAL_TSP_Filein_Addr()
2364 REG32_W(&_RegCtrl2->CFG_35_36, phyMiuOffsetFileinAddr); in HAL_TSP_Filein_Addr()
2368 REG32_W(&_RegCtrl2->CFG_3A_3B, phyMiuOffsetFileinAddr); in HAL_TSP_Filein_Addr()
2383 REG32_W(&_RegCtrl2->CFG_32_33, size); in HAL_TSP_Filein_Size()
2386 REG32_W(&_RegCtrl2->CFG_37_38, size); in HAL_TSP_Filein_Size()
2389 REG32_W(&_RegCtrl2->CFG_3C_3D, size); in HAL_TSP_Filein_Size()
2404 REG16_SET(&_RegCtrl2->CFG_34, CFG_34_REG_TSP_FILEIN_CTRL_TSIF1_START); in HAL_TSP_Filein_Start()
2407 REG16_SET(&_RegCtrl2->CFG_39, CFG_39_FILEIN_CTRL_TSIF2_START); in HAL_TSP_Filein_Start()
2410 REG16_SET(&_RegCtrl2->CFG_3E, CFG_3E_FILEIN_CTRL_TSIF3_START); in HAL_TSP_Filein_Start()
2467 …REG16_SET(&_RegCtrl2->CFG_34, (CFG_34_REG_TSP_FILEIN_INIT_TRUST_TSIF1 | CFG_34_REG_TSP_FILEIN_CTRL… in HAL_TSP_Filein_Init_Trust_Start()
2470 … REG16_SET(&_RegCtrl2->CFG_39, (CFG_39_FILEIN_INIT_TRUST_TSIF2 | CFG_39_FILEIN_CTRL_TSIF2_START)); in HAL_TSP_Filein_Init_Trust_Start()
2473 … REG16_SET(&_RegCtrl2->CFG_3E, (CFG_3E_FILEIN_INIT_TRUST_TSIF3 | CFG_3E_FILEIN_CTRL_TSIF3_START)); in HAL_TSP_Filein_Init_Trust_Start()
2487 REG16_SET(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF0); in HAL_TSP_Filein_Abort()
2490 REG16_SET(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF1); in HAL_TSP_Filein_Abort()
2493 REG16_SET(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF2); in HAL_TSP_Filein_Abort()
2496 REG16_SET(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF3); in HAL_TSP_Filein_Abort()
2507 REG16_CLR(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF0); in HAL_TSP_Filein_Abort()
2510 REG16_CLR(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF1); in HAL_TSP_Filein_Abort()
2513 REG16_CLR(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF2); in HAL_TSP_Filein_Abort()
2516 REG16_CLR(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF3); in HAL_TSP_Filein_Abort()
2534 REG16_SET(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1); in HAL_TSP_Filein_CmdQRst()
2537 REG16_SET(&_RegCtrl2->CFG_05, CFG_05_RST_CMDQ_FILEIN_TSIF2); in HAL_TSP_Filein_CmdQRst()
2540 REG16_SET(&_RegCtrl2->CFG_0A, CFG_0A_RST_CMDQ_FILEIN_TSIF3); in HAL_TSP_Filein_CmdQRst()
2554 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1); in HAL_TSP_Filein_CmdQRst()
2557 REG16_CLR(&_RegCtrl2->CFG_05, CFG_05_RST_CMDQ_FILEIN_TSIF2); in HAL_TSP_Filein_CmdQRst()
2560 REG16_CLR(&_RegCtrl2->CFG_0A, CFG_0A_RST_CMDQ_FILEIN_TSIF3); in HAL_TSP_Filein_CmdQRst()
2575 …return (CFG_3F_REG_TSIF1_CMD_QUEUE_SIZE - (REG16_R(&_RegCtrl2->CFG_3F) & CFG_3F_REG_TSIF1_CMD_QUEU… in HAL_TSP_Filein_CmdQSlot()
2577 …return (CFG_40_REG_TSIF2_CMD_QUEUE_SIZE - (REG16_R(&_RegCtrl2->CFG_40) & CFG_40_REG_TSIF2_CMD_QUEU… in HAL_TSP_Filein_CmdQSlot()
2579 …return (CFG_41_REG_TSIF3_CMD_QUEUE_SIZE - (REG16_R(&_RegCtrl2->CFG_41) & CFG_41_REG_TSIF3_CMD_QUEU… in HAL_TSP_Filein_CmdQSlot()
2593 return (REG16_R(&_RegCtrl2->CFG_3F) & CFG_3F_REG_TSIF1_CMD_QUEUE_WR_CNT); in HAL_TSP_Filein_CmdQCnt()
2595 return (REG16_R(&_RegCtrl2->CFG_40) & CFG_40_REG_TSIF2_CMD_QUEUE_WR_CNT); in HAL_TSP_Filein_CmdQCnt()
2597 return (REG16_R(&_RegCtrl2->CFG_41) & CFG_41_REG_TSIF3_CMD_QUEUE_WR_CNT); in HAL_TSP_Filein_CmdQCnt()
2610 …return ((REG16_R(&_RegCtrl2->CFG_3F) & CFG_3F_REG_TSIF1_CMD_QUEUE_WR_LEVEL) >> CFG_3F_REG_TSIF1_CM… in HAL_TSP_Filein_CmdQLv()
2612 …return ((REG16_R(&_RegCtrl2->CFG_40) & CFG_40_REG_TSIF2_CMD_QUEUE_WR_LEVEL) >> CFG_3F_REG_TSIF1_CM… in HAL_TSP_Filein_CmdQLv()
2614 …return ((REG16_R(&_RegCtrl2->CFG_41) & CFG_41_REG_TSIF3_CMD_QUEUE_WR_LEVEL) >> CFG_3F_REG_TSIF1_CM… in HAL_TSP_Filein_CmdQLv()
2631 REG16_W(&_RegCtrl2->CFG_03, delay & CFG_03_TSP_FILE_TIMER1); in HAL_TSP_Filein_ByteDelay()
2632 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_TIMER_EN1); in HAL_TSP_Filein_ByteDelay()
2635 REG16_W(&_RegCtrl2->CFG_08, delay & CFG_08_TSP_FILE_TIMER2); in HAL_TSP_Filein_ByteDelay()
2636 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_TSP_TIMER_EN2); in HAL_TSP_Filein_ByteDelay()
2639 REG16_W(&_RegCtrl2->CFG_0D, delay & CFG_0D_TSP_FILE_TIMER3); in HAL_TSP_Filein_ByteDelay()
2640 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_TIMER_EN3); in HAL_TSP_Filein_ByteDelay()
2655 REG16_CLR(&_RegCtrl2->CFG_01, CFG_01_TIMER_EN1); in HAL_TSP_Filein_ByteDelay()
2656 REG16_W(&_RegCtrl2->CFG_03, 0x0000); in HAL_TSP_Filein_ByteDelay()
2659 REG16_CLR(&_RegCtrl2->CFG_06, CFG_06_TSP_TIMER_EN2); in HAL_TSP_Filein_ByteDelay()
2660 REG16_W(&_RegCtrl2->CFG_08, 0x0000); in HAL_TSP_Filein_ByteDelay()
2663 REG16_CLR(&_RegCtrl2->CFG_0B, CFG_0B_TIMER_EN3); in HAL_TSP_Filein_ByteDelay()
2664 REG16_W(&_RegCtrl2->CFG_0D, 0x0000); in HAL_TSP_Filein_ByteDelay()
2679 return !(REG16_R(&_RegCtrl2->CFG_34) & CFG_34_REG_TSP_FILEIN_CTRL_TSIF1_DONE); in HAL_TSP_Filein_Status()
2681 return !(REG16_R(&_RegCtrl2->CFG_39) & CFG_39_FILEIN_CTRL_TSIF2_DONE); in HAL_TSP_Filein_Status()
2683 return !(REG16_R(&_RegCtrl2->CFG_3E) & CFG_3E_FILEIN_CTRL_TSIF3_DONE); in HAL_TSP_Filein_Status()
2779 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_PKT192_EN1); in HAL_TSP_Filein_PacketMode()
2782 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_TSP_PKT192_EN2); in HAL_TSP_Filein_PacketMode()
2785 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_PKT192_EN3); in HAL_TSP_Filein_PacketMode()
2799 REG16_CLR(&_RegCtrl2->CFG_01, CFG_01_PKT192_EN1); in HAL_TSP_Filein_PacketMode()
2802 REG16_CLR(&_RegCtrl2->CFG_06, CFG_06_TSP_PKT192_EN2); in HAL_TSP_Filein_PacketMode()
2805 REG16_CLR(&_RegCtrl2->CFG_0B, CFG_0B_PKT192_EN3); in HAL_TSP_Filein_PacketMode()
2824 REG16_CLR(&_RegCtrl2->CFG_01, CFG_01_PKT192_BLK_DISABLE1); in HAL_TSP_Filein_BlockTimeStamp()
2827 REG16_CLR(&_RegCtrl2->CFG_06, CFG_06_TSP_PKT192_BLK_DISABLE2); in HAL_TSP_Filein_BlockTimeStamp()
2830 REG16_CLR(&_RegCtrl2->CFG_0B, CFG_0B_PKT192_BLK_DISABLE3); in HAL_TSP_Filein_BlockTimeStamp()
2843 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_PKT192_BLK_DISABLE1); in HAL_TSP_Filein_BlockTimeStamp()
2846 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_TSP_PKT192_BLK_DISABLE2); in HAL_TSP_Filein_BlockTimeStamp()
2849 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_PKT192_BLK_DISABLE3); in HAL_TSP_Filein_BlockTimeStamp()
2898 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_LPCR2_WLD1); in HAL_TSP_Filein_SetTimeStamp()
2899 REG32_W(&_RegCtrl2->CFG_50_51, u32Stamp); in HAL_TSP_Filein_SetTimeStamp()
2900 REG16_CLR(&_RegCtrl2->CFG_01, CFG_01_LPCR2_WLD1); in HAL_TSP_Filein_SetTimeStamp()
2903 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_LPCR2_WLD2); in HAL_TSP_Filein_SetTimeStamp()
2904 REG32_W(&_RegCtrl2->CFG_52_53, u32Stamp); in HAL_TSP_Filein_SetTimeStamp()
2905 REG16_CLR(&_RegCtrl2->CFG_06, CFG_06_LPCR2_WLD2); in HAL_TSP_Filein_SetTimeStamp()
2908 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_LPCR2_WLD3); in HAL_TSP_Filein_SetTimeStamp()
2909 REG32_W(&_RegCtrl2->CFG_54_55, u32Stamp); in HAL_TSP_Filein_SetTimeStamp()
2910 REG16_CLR(&_RegCtrl2->CFG_0B, CFG_0B_LPCR2_WLD3); in HAL_TSP_Filein_SetTimeStamp()
2980 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_LPCR2_LOAD_TSIF1); in HAL_TSP_Filein_GetTimeStamp()
2981 u32Stamp = REG32_R(&_RegCtrl2->CFG_50_51); in HAL_TSP_Filein_GetTimeStamp()
2982 REG16_SET(&_RegCtrl2->CFG_00, CFG_00_LPCR2_LOAD_TSIF1); in HAL_TSP_Filein_GetTimeStamp()
2985 REG16_CLR(&_RegCtrl2->CFG_05, CFG_05_LPCR2_LOAD_TSIF2); in HAL_TSP_Filein_GetTimeStamp()
2986 u32Stamp = REG32_R(&_RegCtrl2->CFG_52_53); in HAL_TSP_Filein_GetTimeStamp()
2987 REG16_SET(&_RegCtrl2->CFG_05, CFG_05_LPCR2_LOAD_TSIF2); in HAL_TSP_Filein_GetTimeStamp()
2990 REG16_CLR(&_RegCtrl2->CFG_0A, CFG_0A_LPCR2_LOAD_TSIF3); in HAL_TSP_Filein_GetTimeStamp()
2991 u32Stamp = REG32_R(&_RegCtrl2->CFG_54_55); in HAL_TSP_Filein_GetTimeStamp()
2992 REG16_SET(&_RegCtrl2->CFG_0A, CFG_0A_LPCR2_LOAD_TSIF3); in HAL_TSP_Filein_GetTimeStamp()
3008 return REG32_R(&_RegCtrl2->CFG_42_43); in HAL_TSP_Filein_PktTimeStamp()
3010 return REG32_R(&_RegCtrl2->CFG_44_45); in HAL_TSP_Filein_PktTimeStamp()
3012 return REG32_R(&_RegCtrl2->CFG_46_47); in HAL_TSP_Filein_PktTimeStamp()
3027 *pu32Addr = (MS_PHY)(REG32_R(&_RegCtrl2->CFG_6A_6B) & CFG_6A_6B_TSP2MI_RADDR_S_TSIF1); in HAL_TSP_Filein_GetCurAddr()
3030 *pu32Addr = (MS_PHY)(REG32_R(&_RegCtrl2->CFG_6C_6D) & CFG_6C_6D_TSP2MI_RADDR_S_TSIF2); in HAL_TSP_Filein_GetCurAddr()
3033 *pu32Addr = (MS_PHY)(REG32_R(&_RegCtrl2->CFG_6E_6F) & CFG_6E_6F_TSP2MI_RADDR_S_TSIF3); in HAL_TSP_Filein_GetCurAddr()
3097 REG16_W(&_RegCtrl2->CFG_75, (u32Key & CFG_75_FI_MOBF_INDEC_TSIF1_MASK)); in HAL_TSP_Filein_MOBF_Enable()
3100 REG16_W(&_RegCtrl2->CFG_76, (u32Key & CFG_76_FI_MOBF_INDEC_TSIF2_MASK)); in HAL_TSP_Filein_MOBF_Enable()
3103 REG16_W(&_RegCtrl2->CFG_77, (u32Key & CFG_77_FI_MOBF_INDEC_TSIF3_MASK)); in HAL_TSP_Filein_MOBF_Enable()
3117 REG16_W(&_RegCtrl2->CFG_75, 0); in HAL_TSP_Filein_MOBF_Enable()
3120 REG16_W(&_RegCtrl2->CFG_76, 0); in HAL_TSP_Filein_MOBF_Enable()
3123 REG16_W(&_RegCtrl2->CFG_77, 0); in HAL_TSP_Filein_MOBF_Enable()
3581 REG16_MSK_W(&_RegCtrl2->CFG_01, CFG_01_PCR0_SRC_MASK, src << CFG_01_PCR0_SRC_SHIFT); in HAL_TSP_PcrFlt_SetSrc()
3585 REG16_MSK_W(&_RegCtrl2->CFG_01, CFG_01_PCR1_SRC_MASK, src << CFG_01_PCR1_SRC_SHIFT); in HAL_TSP_PcrFlt_SetSrc()
3628 … *pPcrSrc = (REG16_R(&_RegCtrl2->CFG_01) & CFG_01_PCR0_SRC_MASK) >> CFG_01_PCR0_SRC_SHIFT; in HAL_TSP_PcrFlt_GetSrc()
3632 … *pPcrSrc = (REG16_R(&_RegCtrl2->CFG_01) & CFG_01_PCR1_SRC_MASK) >> CFG_01_PCR1_SRC_SHIFT; in HAL_TSP_PcrFlt_GetSrc()
4225 return REG16_R(&_RegCtrl2->CFG_70) & CFG_70_MATCHECED_VPID_3D_MASK; in HAL_TSP_FIFO_PidHit()
4229 return REG16_R(&_RegCtrl2->CFG_71) & CFG_71_MATCHECED_APID_B_MASK; in HAL_TSP_FIFO_PidHit()
4231 return REG16_R(&_RegCtrl2->CFG_74) & CFG_74_MATCHECED_APID_C_MASK; in HAL_TSP_FIFO_PidHit()
4233 return REG16_R(&_RegCtrl2->CFG_7C) & CFG_7C_MATCHECED_APID_D_MASK; in HAL_TSP_FIFO_PidHit()
4832 REG16_MSK_W(&(_RegCtrl2->CFG_15), CFG_15_PVR3_SRC, pktDmxId << CFG_15_PVR3_SRC_SHIFT); in HAL_PVR_Init()
4833 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PVR3_REG_PINGPONG_EN); in HAL_PVR_Init()
4837 REG16_MSK_W(&(_RegCtrl2->CFG_15), CFG_15_PVR4_SRC, pktDmxId << CFG_15_PVR4_SRC_SHIFT); in HAL_PVR_Init()
4838 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_PVR4_REG_PINGPONG_EN); in HAL_PVR_Init()
4870 REG16_CLR(&(_RegCtrl2->CFG_15), CFG_15_PVR3_SRC); in HAL_PVR_Exit()
4871 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_PVR3_REG_PINGPONG_EN); in HAL_PVR_Exit()
4874 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_RST_WADR); in HAL_PVR_Exit()
4875 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_RST_WADR); in HAL_PVR_Exit()
4879 REG16_CLR(&(_RegCtrl2->CFG_15), CFG_15_PVR4_SRC); in HAL_PVR_Exit()
4880 REG16_CLR(&(_RegCtrl2->CFG_23), CFG_23_PVR4_REG_PINGPONG_EN); in HAL_PVR_Exit()
4883 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_RST_WADR); in HAL_PVR_Exit()
4884 REG16_CLR(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_RST_WADR); in HAL_PVR_Exit()
4917 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_RST_WADR); in HAL_PVR_Start()
4918 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_RST_WADR); in HAL_PVR_Start()
4921 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_EN); in HAL_PVR_Start()
4925 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_RST_WADR); in HAL_PVR_Start()
4926 REG16_CLR(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_RST_WADR); in HAL_PVR_Start()
4929 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_EN); in HAL_PVR_Start()
4948 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_EN); in HAL_PVR_Stop()
4952 REG16_CLR(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_EN); in HAL_PVR_Stop()
4972 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_PAUSE); in HAL_PVR_Pause()
4975 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_PAUSE); in HAL_PVR_Pause()
4992 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_PAUSE); in HAL_PVR_Pause()
4995 REG16_CLR(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_PAUSE); in HAL_PVR_Pause()
5018 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PID_BYPASS3_REC); in HAL_PVR_RecPid()
5019 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_REC_ALL3); in HAL_PVR_RecPid()
5022 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_PID_BYPASS4_REC); in HAL_PVR_RecPid()
5023 REG16_CLR(&(_RegCtrl2->CFG_23), CFG_23_REC_ALL4); in HAL_PVR_RecPid()
5042 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_PID_BYPASS3_REC); in HAL_PVR_RecPid()
5043 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_REC_ALL3); in HAL_PVR_RecPid()
5046 REG16_CLR(&(_RegCtrl2->CFG_23), CFG_23_PID_BYPASS4_REC); in HAL_PVR_RecPid()
5047 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_REC_ALL4); in HAL_PVR_RecPid()
5121 … REG32_W(&(_RegCtrl2->CFG_17_18), (phyMiuOffsetPvrBuf0 >> MIU_BUS) & CFG_17_18_PVR3_STR2MI_HEAD); in HAL_PVR_SetBuf()
5123 REG32_W(&(_RegCtrl2->CFG_1B_1C), (u32EndAddr0 >> MIU_BUS) & CFG_1B_1C_PVR3_STR2MI_TAIL); in HAL_PVR_SetBuf()
5125 … REG32_W(&(_RegCtrl2->CFG_19_1A), (phyMiuOffsetPvrBuf0 >> MIU_BUS) & CFG_19_1A_PVR3_STR2MI_MID); in HAL_PVR_SetBuf()
5128 … REG32_W(&(_RegCtrl2->CFG_1D_1E), (phyMiuOffsetPvrBuf1 >> MIU_BUS) & CFG_1D_1E_PVR3_STR2MI_HEAD2); in HAL_PVR_SetBuf()
5130 … REG32_W(&(_RegCtrl2->CFG_21_22), (u32EndAddr1 >> MIU_BUS) & CFG_21_22_PVR3_STR2MI_TAIL2); in HAL_PVR_SetBuf()
5132 … REG32_W(&(_RegCtrl2->CFG_1F_20), (phyMiuOffsetPvrBuf1 >> MIU_BUS) & CFG_1F_20_PVR3_STR2MI_MID2); in HAL_PVR_SetBuf()
5139 … REG32_W(&(_RegCtrl2->CFG_24_25), (phyMiuOffsetPvrBuf0>>MIU_BUS) & CFG_24_25_PVR4_STR2MI_HEAD); in HAL_PVR_SetBuf()
5141 REG32_W(&(_RegCtrl2->CFG_28_29), (u32EndAddr0>>MIU_BUS) & CFG_28_29_PVR4_STR2MI_TAIL); in HAL_PVR_SetBuf()
5143 … REG32_W(&(_RegCtrl2->CFG_26_27), (phyMiuOffsetPvrBuf0>>MIU_BUS) & CFG_26_27_PVR4_STR2MI_MID); in HAL_PVR_SetBuf()
5146 … REG32_W(&(_RegCtrl2->CFG_2A_2B), (phyMiuOffsetPvrBuf1>>MIU_BUS) & CFG_2A_2B_PVR4_STR2MI_HEAD2); in HAL_PVR_SetBuf()
5148 REG32_W(&(_RegCtrl2->CFG_2E_2F), (u32EndAddr1>>MIU_BUS) & CFG_2E_2F_PVR4_STR2MI_TAIL2); in HAL_PVR_SetBuf()
5150 … REG32_W(&(_RegCtrl2->CFG_2C_2D), (phyMiuOffsetPvrBuf1>>MIU_BUS) & CFG_2C_2D_PVR4_STR2MI_MID2); in HAL_PVR_SetBuf()
5180 REG32_W(&(_RegCtrl2->CFG_17_18), (u32StartAddr0>>MIU_BUS) & CFG_17_18_PVR3_STR2MI_HEAD); in HAL_PVR_SetStr2Miu_StartAddr()
5183 … REG32_W(&(_RegCtrl2->CFG_1D_1E), (u32StartAddr1>>MIU_BUS) & CFG_1D_1E_PVR3_STR2MI_HEAD2); in HAL_PVR_SetStr2Miu_StartAddr()
5187 REG32_W(&(_RegCtrl2->CFG_24_25), (u32StartAddr0>>MIU_BUS) & CFG_24_25_PVR4_STR2MI_HEAD); in HAL_PVR_SetStr2Miu_StartAddr()
5190 … REG32_W(&(_RegCtrl2->CFG_2A_2B), (u32StartAddr1>>MIU_BUS) & CFG_2A_2B_PVR4_STR2MI_HEAD2); in HAL_PVR_SetStr2Miu_StartAddr()
5217 REG32_W(&(_RegCtrl2->CFG_19_1A), (u32MidAddr0>>4) & CFG_19_1A_PVR3_STR2MI_MID); in HAL_PVR_SetStr2Miu_MidAddr()
5220 REG32_W(&(_RegCtrl2->CFG_1F_20), (u32MidAddr1>>4) & CFG_1F_20_PVR3_STR2MI_MID2); in HAL_PVR_SetStr2Miu_MidAddr()
5224 REG32_W(&(_RegCtrl2->CFG_26_27), (u32MidAddr0>>4) & CFG_26_27_PVR4_STR2MI_MID); in HAL_PVR_SetStr2Miu_MidAddr()
5227 REG32_W(&(_RegCtrl2->CFG_2C_2D), (u32MidAddr1>>4) & CFG_2C_2D_PVR4_STR2MI_MID2); in HAL_PVR_SetStr2Miu_MidAddr()
5254 REG32_W(&(_RegCtrl2->CFG_1B_1C), (u32EndAddr0>>MIU_BUS) & CFG_1B_1C_PVR3_STR2MI_TAIL); in HAL_PVR_SetStr2Miu_EndAddr()
5257 REG32_W(&(_RegCtrl2->CFG_21_22), (u32EndAddr1>>MIU_BUS) & CFG_21_22_PVR3_STR2MI_TAIL2); in HAL_PVR_SetStr2Miu_EndAddr()
5261 REG32_W(&(_RegCtrl2->CFG_28_29), (u32EndAddr0>>MIU_BUS) & CFG_28_29_PVR4_STR2MI_TAIL); in HAL_PVR_SetStr2Miu_EndAddr()
5264 REG32_W(&(_RegCtrl2->CFG_2E_2F), (u32EndAddr1>>MIU_BUS) & CFG_2E_2F_PVR4_STR2MI_TAIL2); in HAL_PVR_SetStr2Miu_EndAddr()
5282 return (REG32_R(&(_RegCtrl2->CFG_66_67)) << MIU_BUS); in HAL_PVR_GetWritePtr()
5285 return (REG32_R(&(_RegCtrl2->CFG_68_69)) << MIU_BUS); in HAL_PVR_GetWritePtr()
5312 *eSrc = ((REG16_R(&(_RegCtrl2->CFG_15 )) & CFG_15_PVR3_SRC) >> CFG_15_PVR3_SRC_SHIFT); in HAL_PVR_GetEngSrc()
5316 *eSrc = ((REG16_R(&(_RegCtrl2->CFG_15 )) & CFG_15_PVR4_SRC) >> CFG_15_PVR4_SRC_SHIFT); in HAL_PVR_GetEngSrc()
5560 REG16_SET((&_RegCtrl2->CFG_16), CFG_16_PVR3_PKT192_EN); in HAL_PVR_SetStrPacketMode()
5563 REG16_SET((&_RegCtrl2->CFG_23), CFG_23_PVR4_PKT192_EN); in HAL_PVR_SetStrPacketMode()
5580 REG16_CLR((&_RegCtrl2->CFG_16), CFG_16_PVR3_PKT192_EN); in HAL_PVR_SetStrPacketMode()
5583 REG16_CLR((&_RegCtrl2->CFG_23), CFG_23_PVR4_PKT192_EN); in HAL_PVR_SetStrPacketMode()
5612 REG16_CLR((&_RegCtrl2->CFG_16), CFG_16_PVR3_LPCR1_RLD); in HAL_PVR_GetPVRTimeStamp()
5614 u32lpcr = REG32_R((&_RegCtrl2->CFG_62_63)); in HAL_PVR_GetPVRTimeStamp()
5616 REG16_SET((&_RegCtrl2->CFG_16), CFG_16_PVR3_LPCR1_RLD); in HAL_PVR_GetPVRTimeStamp()
5619 REG16_CLR((&_RegCtrl2->CFG_23), CFG_23_PVR4_LPCR1_RLD); in HAL_PVR_GetPVRTimeStamp()
5621 u32lpcr = REG32_R((&_RegCtrl2->CFG_64_65)); in HAL_PVR_GetPVRTimeStamp()
5623 REG16_SET((&_RegCtrl2->CFG_23), CFG_23_PVR4_LPCR1_RLD); in HAL_PVR_GetPVRTimeStamp()
5650 REG16_SET(&_RegCtrl2->CFG_16, CFG_16_PVR3_LPCR1_WLD); in HAL_PVR_SetPVRTimeStamp()
5652 REG32_W((&_RegCtrl2->CFG_62_63), u32Stamp); in HAL_PVR_SetPVRTimeStamp()
5654 REG16_CLR(&_RegCtrl2->CFG_16, CFG_16_PVR3_LPCR1_WLD); in HAL_PVR_SetPVRTimeStamp()
5657 REG16_SET(&_RegCtrl2->CFG_23, CFG_23_PVR4_LPCR1_WLD); in HAL_PVR_SetPVRTimeStamp()
5659 REG32_W((&_RegCtrl2->CFG_64_65), u32Stamp); in HAL_PVR_SetPVRTimeStamp()
5661 REG16_CLR(&_RegCtrl2->CFG_23, CFG_23_PVR4_LPCR1_WLD); in HAL_PVR_SetPVRTimeStamp()
5673 REG16_SET((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD0); in HAL_PVR_SetPVRTimeStamp_Stream()
5675 REG32_W(&_RegCtrl2->CFG_56_57, u32Stamp); in HAL_PVR_SetPVRTimeStamp_Stream()
5677 REG16_CLR((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD0); in HAL_PVR_SetPVRTimeStamp_Stream()
5680 REG16_SET((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD1); in HAL_PVR_SetPVRTimeStamp_Stream()
5682 REG32_W(&_RegCtrl2->CFG_58_59, u32Stamp); in HAL_PVR_SetPVRTimeStamp_Stream()
5684 REG16_CLR((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD1); in HAL_PVR_SetPVRTimeStamp_Stream()
5687 REG16_SET((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD2); in HAL_PVR_SetPVRTimeStamp_Stream()
5689 REG32_W(&_RegCtrl2->CFG_5A_5B, u32Stamp); in HAL_PVR_SetPVRTimeStamp_Stream()
5691 REG16_CLR((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD2); in HAL_PVR_SetPVRTimeStamp_Stream()
5694 REG16_SET((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD3); in HAL_PVR_SetPVRTimeStamp_Stream()
5696 REG32_W(&_RegCtrl2->CFG_5C_5D, u32Stamp); in HAL_PVR_SetPVRTimeStamp_Stream()
5698 REG16_CLR((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD3); in HAL_PVR_SetPVRTimeStamp_Stream()
5718 REG16_SET(&_RegCtrl2->CFG_16, CFG_16_PVR3_PVR_ALIGN_EN); in HAL_PVR_Alignment_Enable()
5721 REG16_SET(&_RegCtrl2->CFG_23, CFG_23_PVR4_PVR_ALIGN_EN); in HAL_PVR_Alignment_Enable()
5738 REG16_CLR(&_RegCtrl2->CFG_16, CFG_16_PVR3_PVR_ALIGN_EN); in HAL_PVR_Alignment_Enable()
5741 REG16_CLR(&_RegCtrl2->CFG_23, CFG_23_PVR4_PVR_ALIGN_EN); in HAL_PVR_Alignment_Enable()
5832 REG16_SET(&_RegCtrl2->CFG_16, CFG_16_PVR3_BLOCK_DIS); in HAL_PVR_Block_Dis()
5835 REG16_SET(&_RegCtrl2->CFG_23, CFG_23_PVR4_BLOCK_DIS); in HAL_PVR_Block_Dis()
5852 REG16_CLR(&_RegCtrl2->CFG_16, CFG_16_PVR3_BLOCK_DIS); in HAL_PVR_Block_Dis()
5855 REG16_CLR(&_RegCtrl2->CFG_23, CFG_23_PVR4_BLOCK_DIS); in HAL_PVR_Block_Dis()
5875 …REG16_MSK_W(&_RegCtrl2->CFG_16, CFG_16_PVR3_BURST_LEN_MASK, (u16BurstMode << CFG_16_PVR3_BURST_LEN… in HAL_PVR_BurstLen()
5878 …REG16_MSK_W(&_RegCtrl2->CFG_23, CFG_23_PVR4_BURST_LEN_MASK, (u16BurstMode << CFG_23_PVR4_BURST_LEN… in HAL_PVR_BurstLen()
5894 REG16_SET((&_RegCtrl2->CFG_12), CFG_12_TIMESTAMP_SEL_PVR1 << (u32PVREng)); in HAL_PVR_TimeStamp_Sel()
5898 REG16_CLR((&_RegCtrl2->CFG_12), CFG_12_TIMESTAMP_SEL_PVR1 << (u32PVREng)); in HAL_PVR_TimeStamp_Sel()
5971 REG16_SET((&_RegCtrl2->CFG_13), CFG_13_LPCR_EN0 << (u32pktDmxId*2)); in HAL_PVR_TimeStamp_Stream_En()
5975 REG16_CLR((&_RegCtrl2->CFG_13), CFG_13_LPCR_EN0 << (u32pktDmxId*2)); in HAL_PVR_TimeStamp_Stream_En()
5990 REG16_W(&_RegCtrl2->CFG_78_7B[0], (u32Key & CFG_78_PVR3_INDEX)); in HAL_PVR_MOBF_Enable()
5993 REG16_W(&_RegCtrl2->CFG_78_7B[2], (u32Key & CFG_78_PVR3_INDEX)); in HAL_PVR_MOBF_Enable()
6295 REG16_MSK_W(&_RegCtrl2->CFG_11, CFG_11_RECEIVE_BUF0_SRC, inputSrc<<(bufIdx * 2)); in HAL_TSP_Set_RcvBuf_Src()
6298 REG16_MSK_W(&_RegCtrl2->CFG_11, CFG_11_RECEIVE_BUF1_SRC, inputSrc<<(bufIdx * 2)); in HAL_TSP_Set_RcvBuf_Src()
6301 REG16_MSK_W(&_RegCtrl2->CFG_11, CFG_11_RECEIVE_BUF2_SRC, inputSrc<<(bufIdx * 2)); in HAL_TSP_Set_RcvBuf_Src()
6304 REG16_MSK_W(&_RegCtrl2->CFG_11, CFG_11_RECEIVE_BUF3_SRC, inputSrc<<(bufIdx * 2)); in HAL_TSP_Set_RcvBuf_Src()