Lines Matching refs:_RegCtrl
45 static REG_Ctrl* _RegCtrl = NULL; // TSP0 and TSP1 variable
166 REG32_W(&_RegCtrl->Idr_Addr, (MS_VIRT)preg); in TSP32_IdrW()
167 REG32_W(&_RegCtrl->Idr_Write, value); in TSP32_IdrW()
168 REG16_W(&_RegCtrl->Idr_Ctrl, TSP_IDR_START | TSP_IDR_WRITE); in TSP32_IdrW()
179 REG32_W(&_RegCtrl->Idr_Addr, (MS_VIRT)preg); in TSP32_IdrR()
180 REG16_W(&_RegCtrl->Idr_Ctrl, TSP_IDR_START | TSP_IDR_READ); in TSP32_IdrR()
182 return REG32_R(&_RegCtrl->Idr_Read); in TSP32_IdrR()
188 _RegCtrl = (REG_Ctrl*) (u32BankAddr + 0x2A00UL); // TSP0 0x1015, TSP1 0x1016 in HAL_TSP_SetBank()
258 REG16_SET(&_RegCtrl->PktChkSizeFilein, TSP_HW_STANDBY_MODE); in HAL_TSP_HwPatch()
263 …REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_BYTE_ADDR_DMA|TSP_HW_CFG4_ALT_TS_SIZE|TSP_HW_CFG4_WST… in HAL_TSP_HwPatch()
269 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_STANDBY); in HAL_TSP_HwPatch()
272 REG16_SET(&_RegCtrl->reg15b4, TSP_PVR_PID_BYPASS|TSP_PVR_PID_BYPASS2); in HAL_TSP_HwPatch()
277 REG16_SET(&_RegCtrl->reg160C, TSP_PVR1_LPCR1_RLD); in HAL_TSP_HwPatch()
278 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_RLD); in HAL_TSP_HwPatch()
282 REG16_SET(&_RegCtrl->reg15b8, TSP_REMOVE_DUP_AV_PKT); in HAL_TSP_HwPatch()
285 …REG16_SET(&_RegCtrl->HW2_Config3, TSP_VQ2PINGPONG_EN | TSP_RM_PKT_DEMUX_PIPE /*| TSP_PVR1_ALIGN_EN… in HAL_TSP_HwPatch()
288 …REG16_SET(&_RegCtrl->reg160C, TSP_DOUBLE_BUF_DESC/*| TSP_VQTX0_BLOCK_DIS|TSP_VQTX2_BLOCK_DIS|TSP_V… in HAL_TSP_HwPatch()
289 REG16_SET(&_RegCtrl->reg160E, TSP_RM_DMA_GLITCH); in HAL_TSP_HwPatch()
293 REG16_SET(&_RegCtrl->TSP_Cfg5, TSP_SYSTIME_MODE); in HAL_TSP_HwPatch()
296 REG16_SET(&_RegCtrl->PVRConfig, TSP_MATCH_PID_LD | TSP_REC_NULL); in HAL_TSP_HwPatch()
304 REG16_SET(&_RegCtrl->reg15b8, TSP_SERIAL_EXT_SYNC_1T); in HAL_TSP_HwPatch()
305 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_SYNC_RISING_DETECT); in HAL_TSP_HwPatch()
306 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_VALID_FALLING_DETECT) in HAL_TSP_HwPatch()
309 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_DATA_CHK_2T); in HAL_TSP_HwPatch()
370 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_PVR_CMD_QUEUE_ENABLE); in HAL_TSP_Reset()
375 REG16_SET(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_CMDQ_RESET); in HAL_TSP_Reset()
379 REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_WB_DMA_RESET); in HAL_TSP_Reset()
380 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_SW_RST); in HAL_TSP_Reset()
384 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_SW_RST); in HAL_TSP_Reset()
386 REG16_CLR(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_WB_DMA_RESET); in HAL_TSP_Reset()
388 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_CMDQ_RESET); in HAL_TSP_Reset()
402 REG16_SET(&_RegCtrl->reg160C,TSP_TIMESTAMP_RESET); in HAL_TSP_Path_Reset()
410 REG16_CLR(&_RegCtrl->reg160C,TSP_TIMESTAMP_RESET); in HAL_TSP_Path_Reset()
647 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_CPU_EN); in HAL_TSP_CPU()
651 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_CPU_EN); in HAL_TSP_CPU()
659 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_CPU_EN); in HAL_TSP_ResetCPU()
663 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_CPU_EN); in HAL_TSP_ResetCPU()
679 REG32_W(&_RegCtrl->Cpu_Base, 0); // 16 bytes address unit in HAL_TSP_LoadFW()
693 … REG16_W(&_RegCtrl->Dnld_Ctrl_Addr, (MS_U16)(u32DnldCtrl & TSP_DNLD_ADDR_MASK)); // oneway register in HAL_TSP_LoadFW()
694 REG16_MSK_W(&_RegCtrl->Dnld_AddrH, TSP_DMA_RADDR_MSB_MASK, (MS_U16)u32DnldCtrl1); in HAL_TSP_LoadFW()
695 REG16_W(&_RegCtrl->Dnld_Ctrl_Size, _TSP_QMEM_SIZE); in HAL_TSP_LoadFW()
696 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_DNLD_START| TSP_CTRL_DNLD_DONE); in HAL_TSP_LoadFW()
697 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_DNLD_START); in HAL_TSP_LoadFW()
701 while (!(REG16_R(&_RegCtrl->TSP_Ctrl) & TSP_CTRL_DNLD_DONE)) in HAL_TSP_LoadFW()
707 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_DNLD_START| TSP_CTRL_DNLD_DONE); in HAL_TSP_LoadFW()
709 REG32_W(&_RegCtrl->Qmem_Imask, _TSP_QMEM_I_MASK); in HAL_TSP_LoadFW()
710 REG32_W(&_RegCtrl->Qmem_Ibase, _TSP_QMEM_I_ADDR_HIT); in HAL_TSP_LoadFW()
711 REG32_W(&_RegCtrl->Qmem_Dmask, _TSP_QMEM_D_MASK); in HAL_TSP_LoadFW()
712 REG32_W(&_RegCtrl->Qmem_Dbase, _TSP_QMEM_D_ADDR_HIT); in HAL_TSP_LoadFW()
873 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TSIF0_ENABLE); in HAL_TSP_TSIF_LiveEn()
876 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TSIF1_ENABLE); in HAL_TSP_TSIF_LiveEn()
879 REG32_SET(&_RegCtrl->PVR2_Config, TSP_TS_IF2_EN); in HAL_TSP_TSIF_LiveEn()
893 REG16_CLR(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TSIF0_ENABLE); in HAL_TSP_TSIF_LiveEn()
896 REG16_CLR(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TSIF1_ENABLE); in HAL_TSP_TSIF_LiveEn()
899 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_TS_IF2_EN); in HAL_TSP_TSIF_LiveEn()
1564 …REG16_SET(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_PVR_CMD_QUEUE_ENABLE); // for wishbone DMA (load firm… in HAL_TSP_TSIF_FileEn()
1565 … REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_DATA_PORT_SEL); //Tsif0 output is live TS in HAL_TSP_TSIF_FileEn()
1566 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_TSFILE_EN); //filein enable in HAL_TSP_TSIF_FileEn()
1595 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_PVR_CMD_QUEUE_ENABLE); in HAL_TSP_TSIF_FileEn()
1596 REG16_CLR(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_DATA_PORT_SEL); in HAL_TSP_TSIF_FileEn()
1597 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_TSFILE_EN); in HAL_TSP_TSIF_FileEn()
1632 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TS_DATA0_SWAP); in HAL_TSP_TSIF_BitSwap()
1635 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TS_DATA1_SWAP); in HAL_TSP_TSIF_BitSwap()
1638 REG32_SET(&_RegCtrl->PVR2_Config, TSP_TS_DATA2_SWAP); in HAL_TSP_TSIF_BitSwap()
1652 REG16_CLR(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TS_DATA0_SWAP); in HAL_TSP_TSIF_BitSwap()
1655 REG16_CLR(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TS_DATA1_SWAP); in HAL_TSP_TSIF_BitSwap()
1658 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_TS_DATA2_SWAP); in HAL_TSP_TSIF_BitSwap()
1678 REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_EXTSYNC); in HAL_TSP_TSIF_ExtSync()
1681 REG16_SET(&_RegCtrl->Hw_Config2, TSP_HW_CFG2_TSIF1_EXTSYNC); in HAL_TSP_TSIF_ExtSync()
1684 REG32_SET(&_RegCtrl->PVR2_Config, TSP_EXT_SYNC_SEL2); in HAL_TSP_TSIF_ExtSync()
1700 REG16_CLR(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_EXTSYNC); in HAL_TSP_TSIF_ExtSync()
1703 REG16_CLR(&_RegCtrl->Hw_Config2, TSP_HW_CFG2_TSIF1_EXTSYNC); in HAL_TSP_TSIF_ExtSync()
1706 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_EXT_SYNC_SEL2); in HAL_TSP_TSIF_ExtSync()
1725 REG16_SET(&(_RegCtrl->TSP_Ctrl2), TSP_AV_DIRECT_STOP);
1728 REG16_SET(&(_RegCtrl->TSP_Ctrl2), TSP_AV_DIRECT_STOP1);
1731 REG16_SET(&(_RegCtrl->TSP_Ctrl2), TSP_AV_DIRECT_STOP2);
1734 REG16_SET(&(_RegCtrl->TSP_Ctrl2), TSP_AV_DIRECT_STOP3);
1745 REG16_CLR(&(_RegCtrl->TSP_Ctrl2), TSP_AV_DIRECT_STOP);
1748 REG16_CLR(&(_RegCtrl->TSP_Ctrl2), TSP_AV_DIRECT_STOP1);
1751 REG16_CLR(&(_RegCtrl->TSP_Ctrl2), TSP_AV_DIRECT_STOP2);
1754 REG16_CLR(&(_RegCtrl->TSP_Ctrl2), TSP_AV_DIRECT_STOP3);
1772 REG16_SET(&_RegCtrl->TSP_Ctrl2, TSP_AV_DIRECT_STOP); in HAL_TSP_Filein_Bypass()
1775 REG16_SET(&_RegCtrl->TSP_Ctrl2, TSP_AV_DIRECT_STOP1); in HAL_TSP_Filein_Bypass()
1778 REG16_SET(&_RegCtrl->TSP_Ctrl2, TSP_AV_DIRECT_STOP2); in HAL_TSP_Filein_Bypass()
1781 REG16_SET(&_RegCtrl->TSP_Ctrl2, TSP_AV_DIRECT_STOP3); in HAL_TSP_Filein_Bypass()
1794 REG16_CLR(&_RegCtrl->TSP_Ctrl2, TSP_AV_DIRECT_STOP); in HAL_TSP_Filein_Bypass()
1797 REG16_CLR(&_RegCtrl->TSP_Ctrl2, TSP_AV_DIRECT_STOP1); in HAL_TSP_Filein_Bypass()
1800 REG16_CLR(&_RegCtrl->TSP_Ctrl2, TSP_AV_DIRECT_STOP2); in HAL_TSP_Filein_Bypass()
1803 REG16_CLR(&_RegCtrl->TSP_Ctrl2, TSP_AV_DIRECT_STOP3); in HAL_TSP_Filein_Bypass()
1820 REG16_SET(&(_RegCtrl->Hw_Config0), TSP_HW_CFG0_TSIF0_PARL); in HAL_TSP_TSIF_Parl()
1823 REG16_SET(&(_RegCtrl->Hw_Config2), TSP_HW_CFG2_TSIF1_PARL); in HAL_TSP_TSIF_Parl()
1826 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_P_SEL2); in HAL_TSP_TSIF_Parl()
1840 REG16_CLR(&(_RegCtrl->Hw_Config0), TSP_HW_CFG0_TSIF0_PARL); in HAL_TSP_TSIF_Parl()
1843 REG16_CLR(&(_RegCtrl->Hw_Config2), TSP_HW_CFG2_TSIF1_PARL); in HAL_TSP_TSIF_Parl()
1846 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_P_SEL2); in HAL_TSP_TSIF_Parl()
2208 REG16_SET(&_RegCtrl->reg15b4, TSP_BD_AUD_EN); in HAL_TSP_BD_AUD_En()
2211 REG16_SET(&_RegCtrl->reg15b4, TSP_BD2_AUD_EN); in HAL_TSP_BD_AUD_En()
2223 REG16_CLR(&_RegCtrl->reg15b4, TSP_BD_AUD_EN); in HAL_TSP_BD_AUD_En()
2226 REG16_CLR(&_RegCtrl->reg15b4, TSP_BD2_AUD_EN); in HAL_TSP_BD_AUD_En()
2328 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_ALT_TS_SIZE); in HAL_TSP_Filein_PktSize()
2329 …REG16_W(&_RegCtrl->PktChkSizeFilein, (REG16_R(&_RegCtrl->PktChkSizeFilein) & ~TSP_PKT_SIZE_MASK) |… in HAL_TSP_Filein_PktSize()
2356 REG32_W(&_RegCtrl->TsDma_Addr, phyMiuOffsetFileinAddr); in HAL_TSP_Filein_Addr()
2380 REG32_W(&_RegCtrl->TsDma_Size, size); in HAL_TSP_Filein_Size()
2401 REG16_SET(&_RegCtrl->TsDma_Ctrl, TSP_TSDMA_CTRL_START); in HAL_TSP_Filein_Start()
2422 REG16_SET(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_FILEIN_PAUSE); in HAL_TSP_File_Pause()
2443 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_FILEIN_PAUSE); in HAL_TSP_File_Resume()
2464 REG16_SET(&_RegCtrl->TsDma_Ctrl, (TSP_TSDMA_INIT_TRUST | TSP_TSDMA_CTRL_START)); in HAL_TSP_Filein_Init_Trust_Start()
2531 REG16_SET(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_CMDQ_RESET); in HAL_TSP_Filein_CmdQRst()
2551 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_CMDQ_RESET); in HAL_TSP_Filein_CmdQRst()
2573 …return (TSP_CMDQ_SIZE - ((REG16_R(&_RegCtrl->TsDma_mdQ) & TSP_CMDQ_CNT_MASK) >> TSP_CMDQ_CNT_SHFT)… in HAL_TSP_Filein_CmdQSlot()
2591 return ((REG16_R(&_RegCtrl->TsDma_mdQ) & TSP_CMDQ_CNT_MASK) >> TSP_CMDQ_CNT_SHFT); in HAL_TSP_Filein_CmdQCnt()
2608 … return ((REG16_R(&_RegCtrl->TsDma_Ctrl) & TSP_CMDQ_WR_LEVEL_MASK) >> TSP_CMDQ_WR_LEVEL_SHFT); in HAL_TSP_Filein_CmdQLv()
2627 REG32_W(&_RegCtrl->TsFileIn_Timer, delay & TSP_FILE_TIMER_MASK); in HAL_TSP_Filein_ByteDelay()
2628 REG16_SET(&_RegCtrl->reg15b4, TSP_FILEIN_BYTETIMER_ENABLE); in HAL_TSP_Filein_ByteDelay()
2651 REG16_CLR(&_RegCtrl->reg15b4, TSP_FILEIN_BYTETIMER_ENABLE); in HAL_TSP_Filein_ByteDelay()
2652 REG32_W(&_RegCtrl->TsFileIn_Timer, 0x0000); in HAL_TSP_Filein_ByteDelay()
2677 return !(REG16_R(&_RegCtrl->TsDma_Ctrl) & TSP_TSDMA_FILEIN_DONE); in HAL_TSP_Filein_Status()
2707 if (REG16_R(&_RegCtrl->TSP_Ctrl1) & TSP_CTRL1_FILEIN_PAUSE ) in HAL_TSP_Filein_GetState()
2776 REG16_SET(&_RegCtrl->reg160C, TSP_FILEIN192_EN); in HAL_TSP_Filein_PacketMode()
2796 REG16_CLR(&_RegCtrl->reg160C, TSP_FILEIN192_EN); in HAL_TSP_Filein_PacketMode()
2821 REG16_CLR(&_RegCtrl->PktChkSizeFilein, TSP_PKT192_BLK_DIS_FIN); in HAL_TSP_Filein_BlockTimeStamp()
2840 REG16_SET(&_RegCtrl->PktChkSizeFilein, TSP_PKT192_BLK_DIS_FIN); in HAL_TSP_Filein_BlockTimeStamp()
2893 REG16_SET(&_RegCtrl->reg160C, TSP_LPCR2_WLD); in HAL_TSP_Filein_SetTimeStamp()
2894 REG32_W(&_RegCtrl->LPcr2, u32Stamp); in HAL_TSP_Filein_SetTimeStamp()
2895 REG16_CLR(&_RegCtrl->reg160C, TSP_LPCR2_WLD); in HAL_TSP_Filein_SetTimeStamp()
2975 REG16_CLR(&_RegCtrl->reg160C, TSP_LPCR2_RLD); in HAL_TSP_Filein_GetTimeStamp()
2976 u32Stamp = REG32_R(&_RegCtrl->LPcr2); in HAL_TSP_Filein_GetTimeStamp()
2977 REG16_SET(&_RegCtrl->reg160C, TSP_LPCR2_RLD); in HAL_TSP_Filein_GetTimeStamp()
3006 return REG32_R(&_RegCtrl->TimeStamp_FileIn); in HAL_TSP_Filein_PktTimeStamp()
3024 *pu32Addr = (MS_PHY)(REG32_R(&_RegCtrl->TsFileIn_RPtr) & TSP_FILE_RPTR_MASK); in HAL_TSP_Filein_GetCurAddr()
3094 REG16_W(&_RegCtrl->Mobf_Filein_Idx, (u32Key & TSP_MOBF_FILEIN_MASK)); in HAL_TSP_Filein_MOBF_Enable()
3114 REG16_W(&_RegCtrl->Mobf_Filein_Idx, 0); in HAL_TSP_Filein_MOBF_Enable()
3217 REG16_SET(&_RegCtrl->TSP_Cfg5, TSP_SEC_DMA_BURST_EN); in HAL_TSP_SecFlt_BurstLen()
3218 REG16_MSK_W(&_RegCtrl->Hw_Config4, TSP_HW_DMA_MODE_MASK, (burstMode << TSP_HW_DMA_MODE_SHIFT)); in HAL_TSP_SecFlt_BurstLen()
3493 REG16_SET(&_RegCtrl->PIDFLT_PCR0, TSP_PIDFLT_PCR0_EN); in HAL_TSP_PcrFlt_Enable()
3497 REG16_CLR(&_RegCtrl->PIDFLT_PCR0, TSP_PIDFLT_PCR0_EN); in HAL_TSP_PcrFlt_Enable()
3503 REG16_SET(&_RegCtrl->PIDFLT_PCR1, TSP_PIDFLT_PCR1_EN); in HAL_TSP_PcrFlt_Enable()
3507 REG16_CLR(&_RegCtrl->PIDFLT_PCR1, TSP_PIDFLT_PCR1_EN); in HAL_TSP_PcrFlt_Enable()
3540 REG16_MSK_W(&_RegCtrl->PIDFLT_PCR0, TSP_PIDFLT_PCR0_PID_MASK, u32Pid); in HAL_TSP_PcrFlt_SetPid()
3543 REG16_MSK_W(&_RegCtrl->PIDFLT_PCR1, TSP_PIDFLT_PCR1_PID_MASK, u32Pid); in HAL_TSP_PcrFlt_SetPid()
3562 return (REG16_R(&_RegCtrl->PIDFLT_PCR0) & TSP_PIDFLT_PCR0_PID_MASK); in HAL_TSP_PcrFlt_GetPid()
3564 return (REG16_R(&_RegCtrl->PIDFLT_PCR1) & TSP_PIDFLT_PCR1_PID_MASK); in HAL_TSP_PcrFlt_GetPid()
3690 REG16_SET(&_RegCtrl->PCR_Cfg, TSP_PCR0_READ); in HAL_TSP_PcrFlt_GetPcr()
3691 *pu32Pcr = REG32_R(&_RegCtrl->HWPCR0_L); in HAL_TSP_PcrFlt_GetPcr()
3692 *pu32Pcr_H = REG32_R(&_RegCtrl->HWPCR0_H) & 0x1; in HAL_TSP_PcrFlt_GetPcr()
3693 REG16_CLR(&_RegCtrl->PCR_Cfg, TSP_PCR0_READ); in HAL_TSP_PcrFlt_GetPcr()
3696 REG16_SET(&_RegCtrl->PCR_Cfg, TSP_PCR1_READ); in HAL_TSP_PcrFlt_GetPcr()
3697 *pu32Pcr = REG32_R(&_RegCtrl->HWPCR1_L); in HAL_TSP_PcrFlt_GetPcr()
3698 *pu32Pcr_H = REG32_R(&_RegCtrl->HWPCR1_H) & 0x1; in HAL_TSP_PcrFlt_GetPcr()
3699 REG16_CLR(&_RegCtrl->PCR_Cfg, TSP_PCR1_READ); in HAL_TSP_PcrFlt_GetPcr()
3724 REG16_CLR(&_RegCtrl->PCR_Cfg, TSP_PCR0_RESET); in HAL_TSP_PcrFlt_Reset()
3725 REG16_SET(&_RegCtrl->PCR_Cfg, TSP_PCR0_RESET); in HAL_TSP_PcrFlt_Reset()
3728 REG16_CLR(&_RegCtrl->PCR_Cfg, TSP_PCR1_RESET); in HAL_TSP_PcrFlt_Reset()
3729 REG16_SET(&_RegCtrl->PCR_Cfg, TSP_PCR1_RESET); in HAL_TSP_PcrFlt_Reset()
3751 REG16_W(&_RegCtrl->HwInt2_Stat, in HAL_TSP_PcrFlt_ClearInt()
3752 (REG16_R(&_RegCtrl->HwInt2_Stat) & (~TSP_HWINT2_STATUS_MASK)) | in HAL_TSP_PcrFlt_ClearInt()
3757 REG16_W(&_RegCtrl->HwInt2_Stat, in HAL_TSP_PcrFlt_ClearInt()
3758 (REG16_R(&_RegCtrl->HwInt2_Stat) & (~TSP_HWINT2_STATUS_MASK)) | in HAL_TSP_PcrFlt_ClearInt()
3763 REG16_W(&_RegCtrl->HwInt3_Stat, in HAL_TSP_PcrFlt_ClearInt()
3764 (REG16_R(&_RegCtrl->HwInt3_Stat) & (~TSP_HWINT3_STATUS_MASK)) | in HAL_TSP_PcrFlt_ClearInt()
3769 REG16_W(&_RegCtrl->HwInt3_Stat, in HAL_TSP_PcrFlt_ClearInt()
3770 (REG16_R(&_RegCtrl->HwInt3_Stat) & (~TSP_HWINT3_STATUS_MASK)) | in HAL_TSP_PcrFlt_ClearInt()
3891 REG16_SET(&_RegCtrl->TSP_Cfg5, TSP_SYSTIME_MODE); in HAL_TSP_STC64_Mode_En()
3895 REG16_CLR(&_RegCtrl->TSP_Cfg5, TSP_SYSTIME_MODE); in HAL_TSP_STC64_Mode_En()
3904 REG32_W(&_RegCtrl->Pcr_L, stcL); in HAL_TSP_STC64_Set()
3905 REG32_W(&_RegCtrl->Pcr_H, stcH); in HAL_TSP_STC64_Set()
3908 REG32_W(&_RegCtrl->PCR64_2_L, stcL); in HAL_TSP_STC64_Set()
3909 REG32_W(&_RegCtrl->PCR64_2_H, stcH); in HAL_TSP_STC64_Set()
3919 REG16_CLR(&_RegCtrl->reg15b8, TSP_cnt_33b_ld); in HAL_TSP_STC64_Get()
3920 *pStcH = REG32_R(&_RegCtrl->Pcr_H); in HAL_TSP_STC64_Get()
3921 *pStcL = REG32_R(&_RegCtrl->Pcr_L); in HAL_TSP_STC64_Get()
3922 REG16_SET(&_RegCtrl->reg15b8, TSP_cnt_33b_ld); in HAL_TSP_STC64_Get()
3925 REG16_CLR(&_RegCtrl->reg15b8, TSP_64bit_PCR2_ld); in HAL_TSP_STC64_Get()
3926 *pStcH = REG32_R(&_RegCtrl->PCR64_2_H); in HAL_TSP_STC64_Get()
3927 *pStcL = REG32_R(&_RegCtrl->PCR64_2_L); in HAL_TSP_STC64_Get()
3928 REG16_SET(&_RegCtrl->reg15b8, TSP_64bit_PCR2_ld); in HAL_TSP_STC64_Get()
3937 REG16_W(&_RegCtrl->Pcr_H_CmdQ, stcH & TSP_REG_PCR_CMDQ_H); in HAL_TSP_STC33_CmdQSet()
3938 REG32_W(&_RegCtrl->Pcr_L_CmdQ, stcL); in HAL_TSP_STC33_CmdQSet()
3943 REG16_CLR(&_RegCtrl->reg15b8, TSP_cnt_33b_ld); in HAL_TSP_STC33_CmdQGet()
3944 *pStcH = REG16_R(&_RegCtrl->Pcr_H_CmdQ) & TSP_REG_PCR_CMDQ_H; in HAL_TSP_STC33_CmdQGet()
3945 *pStcL = REG32_R(&_RegCtrl->Pcr_L_CmdQ); in HAL_TSP_STC33_CmdQGet()
3946 REG16_SET(&_RegCtrl->reg15b8, TSP_cnt_33b_ld); in HAL_TSP_STC33_CmdQGet()
3954 … REG16_MSK_W(&_RegCtrl->FIFO_Src, TSP_VID_SRC_MASK, ((MS_U16)pktDmxId) << TSP_VID_SRC_SHIFT); in HAL_TSP_FIFO_SetSrc()
3957 … REG16_MSK_W(&_RegCtrl->FIFO_Src, TSP_VID3D_SRC_MASK, ((MS_U16)pktDmxId) << TSP_VID3D_SRC_SHIFT); in HAL_TSP_FIFO_SetSrc()
3960 … REG16_MSK_W(&_RegCtrl->FIFO_Src, TSP_AUD_SRC_MASK, ((MS_U16)pktDmxId) << TSP_AUD_SRC_SHIFT); in HAL_TSP_FIFO_SetSrc()
3963 … REG16_MSK_W(&_RegCtrl->FIFO_Src, TSP_AUDB_SRC_MASK, ((MS_U16)pktDmxId) << TSP_AUDB_SRC_SHIFT); in HAL_TSP_FIFO_SetSrc()
3966 … REG16_MSK_W(&_RegCtrl->PCR_Cfg, TSP_AUDC_SRC_MASK, ((MS_U16)pktDmxId) << TSP_AUDC_SRC_SHIFT); in HAL_TSP_FIFO_SetSrc()
3969 … REG16_MSK_W(&_RegCtrl->PCR_Cfg, TSP_AUDD_SRC_MASK, ((MS_U16)pktDmxId) << TSP_AUDD_SRC_SHIFT); in HAL_TSP_FIFO_SetSrc()
3981 *pktDmxId = ((REG16_R(&_RegCtrl->FIFO_Src)) & TSP_VID_SRC_MASK) >> TSP_VID_SRC_SHIFT; in HAL_TSP_FIFO_GetSrc()
3984 … *pktDmxId = ((REG16_R(&_RegCtrl->FIFO_Src)) & TSP_VID3D_SRC_MASK) >> TSP_VID3D_SRC_SHIFT; in HAL_TSP_FIFO_GetSrc()
3987 *pktDmxId = ((REG16_R(&_RegCtrl->FIFO_Src)) & TSP_AUD_SRC_MASK) >> TSP_AUD_SRC_SHIFT; in HAL_TSP_FIFO_GetSrc()
3990 *pktDmxId = ((REG16_R(&_RegCtrl->FIFO_Src)) & TSP_AUDB_SRC_MASK) >> TSP_AUDB_SRC_SHIFT; in HAL_TSP_FIFO_GetSrc()
3993 *pktDmxId = ((REG16_R(&_RegCtrl->PCR_Cfg)) & TSP_AUDC_SRC_MASK) >> TSP_AUDC_SRC_SHIFT; in HAL_TSP_FIFO_GetSrc()
3996 *pktDmxId = ((REG16_R(&_RegCtrl->PCR_Cfg)) & TSP_AUDD_SRC_MASK) >> TSP_AUDD_SRC_SHIFT; in HAL_TSP_FIFO_GetSrc()
4006 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_VID_EN); in HAL_TSP_FIFO_ClearAll()
4007 REG16_CLR(&_RegCtrl->TSP_Ctrl2, TSP_PS_VID_3D_EN); in HAL_TSP_FIFO_ClearAll()
4008 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUD_EN); in HAL_TSP_FIFO_ClearAll()
4009 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDB_EN); in HAL_TSP_FIFO_ClearAll()
4010 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDC_EN); in HAL_TSP_FIFO_ClearAll()
4011 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDD_EN); in HAL_TSP_FIFO_ClearAll()
4020 REG16_SET(&_RegCtrl->reg15b4,TSP_AVFIFO_RD_EN); in HAL_TSP_FIFO_ReadEn()
4024 REG16_CLR(&_RegCtrl->reg15b4,TSP_AVFIFO_RD_EN); in HAL_TSP_FIFO_ReadEn()
4031 return (REG16_R(&_RegCtrl->PKT_CNT) & TSP_PKT_CNT_MASK); in HAL_TSP_FIFO_ReadPkt()
4073 REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_VPID_BYPASS); in HAL_TSP_Flt_Bypass()
4079 REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_APID_BYPASS); in HAL_TSP_Flt_Bypass()
4099 REG16_CLR(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_VPID_BYPASS); in HAL_TSP_Flt_Bypass()
4105 REG16_CLR(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_APID_BYPASS); in HAL_TSP_Flt_Bypass()
4139 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_VID_EN); in HAL_TSP_FIFO_Bypass()
4142 REG16_SET(&_RegCtrl->TSP_Ctrl2, TSP_PS_VID_3D_EN); in HAL_TSP_FIFO_Bypass()
4145 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUD_EN); in HAL_TSP_FIFO_Bypass()
4148 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDB_EN); in HAL_TSP_FIFO_Bypass()
4151 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDC_EN); in HAL_TSP_FIFO_Bypass()
4154 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDD_EN); in HAL_TSP_FIFO_Bypass()
4165 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_VID_EN); in HAL_TSP_FIFO_Bypass()
4168 REG16_CLR(&_RegCtrl->TSP_Ctrl2, TSP_PS_VID_3D_EN); in HAL_TSP_FIFO_Bypass()
4171 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUD_EN); in HAL_TSP_FIFO_Bypass()
4174 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDB_EN); in HAL_TSP_FIFO_Bypass()
4177 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDC_EN); in HAL_TSP_FIFO_Bypass()
4180 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDD_EN); in HAL_TSP_FIFO_Bypass()
4223 return REG16_R(&_RegCtrl->Vd_Pid_Hit) & TSP_VPID_MASK; in HAL_TSP_FIFO_PidHit()
4227 return REG16_R(&_RegCtrl->Aud_Pid_Hit) & TSP_APID_MASK; in HAL_TSP_FIFO_PidHit()
4246 REG16_SET(&_RegCtrl->reg160E, TSP_RESET_VFIFO); in HAL_TSP_FIFO_Reset()
4249 REG16_SET(&_RegCtrl->reg160E, TSP_RESET_VFIFO3D); in HAL_TSP_FIFO_Reset()
4252 REG16_SET(&_RegCtrl->reg160E, TSP_RESET_AFIFO); in HAL_TSP_FIFO_Reset()
4255 REG16_SET(&_RegCtrl->reg160E, TSP_RESET_AFIFO2); in HAL_TSP_FIFO_Reset()
4258 REG16_SET(&_RegCtrl->reg160E, TSP_RESET_AFIFO3); in HAL_TSP_FIFO_Reset()
4261 REG16_SET(&_RegCtrl->PktChkSizeFilein, TSP_RESET_AFIFO4); in HAL_TSP_FIFO_Reset()
4272 REG16_CLR(&_RegCtrl->reg160E, TSP_RESET_VFIFO); in HAL_TSP_FIFO_Reset()
4275 REG16_CLR(&_RegCtrl->reg160E, TSP_RESET_VFIFO3D); in HAL_TSP_FIFO_Reset()
4278 REG16_CLR(&_RegCtrl->reg160E, TSP_RESET_AFIFO); in HAL_TSP_FIFO_Reset()
4281 REG16_CLR(&_RegCtrl->reg160E, TSP_RESET_AFIFO2); in HAL_TSP_FIFO_Reset()
4284 REG16_CLR(&_RegCtrl->reg160E, TSP_RESET_AFIFO3); in HAL_TSP_FIFO_Reset()
4287 REG16_CLR(&_RegCtrl->PktChkSizeFilein, TSP_RESET_AFIFO4); in HAL_TSP_FIFO_Reset()
4362 REG32_SET(&_RegCtrl->PVR2_Config, TSP_V_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4365 REG32_SET(&_RegCtrl->PVR2_Config, TSP_V3d_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4368 REG32_SET(&_RegCtrl->PVR2_Config, TSP_A_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4371 REG32_SET(&_RegCtrl->PVR2_Config, TSP_AD_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4374 REG32_SET(&_RegCtrl->PVR2_Config, TSP_AC_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4377 REG32_SET(&_RegCtrl->PVR2_Config, TSP_ADD_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4388 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_V_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4391 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_V3d_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4394 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_A_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4397 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_AD_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4400 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_AC_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4403 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_ADD_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4417 u32Matched = REG16_R(&_RegCtrl->reg160E) & TSP_RESET_VFIFO; in HAL_TSP_FIFO_IsReset()
4420 u32Matched = REG16_R(&_RegCtrl->reg160E) & TSP_RESET_VFIFO3D; in HAL_TSP_FIFO_IsReset()
4423 u32Matched = REG16_R(&_RegCtrl->reg160E) & TSP_RESET_AFIFO; in HAL_TSP_FIFO_IsReset()
4426 u32Matched = REG16_R(&_RegCtrl->reg160E) & TSP_RESET_AFIFO2; in HAL_TSP_FIFO_IsReset()
4429 u32Matched = REG16_R(&_RegCtrl->reg160E) & TSP_RESET_AFIFO3; in HAL_TSP_FIFO_IsReset()
4432 u32Matched = REG16_R(&_RegCtrl->PktChkSizeFilein) & TSP_RESET_AFIFO4; in HAL_TSP_FIFO_IsReset()
4478 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_VFIFO_LEVEL) >> TSP_VFIFO_LEVEL_SHFT; in HAL_TSP_FIFO_Level()
4480 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_VFIFO3D_LEVEL) >> TSP_VFIFO3D_LEVEL_SHFT; in HAL_TSP_FIFO_Level()
4482 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_AFIFO_LEVEL) >> TSP_AFIFO_LEVEL_SHFT; in HAL_TSP_FIFO_Level()
4484 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_AFIFOB_LEVEL) >> TSP_AFIFOB_LEVEL_SHFT; in HAL_TSP_FIFO_Level()
4499 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_VFIFO_FULL) >> TSP_VFIFO_FULL_SHFT; in HAL_TSP_FIFO_Overflow()
4501 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_VFIFO3D_FULL) >> TSP_VFIFO3D_FULL_SHFT; in HAL_TSP_FIFO_Overflow()
4503 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_AFIFO_FULL) >> TSP_AFIFO_FULL_SHFT; in HAL_TSP_FIFO_Overflow()
4505 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_AFIFOB_FULL) >> TSP_AFIFOB_FULL_SHFT; in HAL_TSP_FIFO_Overflow()
4520 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_VFIFO_EMPTY) >> TSP_VFIFO_EMPTY_SHFT; in HAL_TSP_FIFO_Empty()
4522 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_VFIFO3D_EMPTY) >> TSP_VFIFO3D_EMPTY_SHFT; in HAL_TSP_FIFO_Empty()
4524 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_AFIFO_EMPTY) >> TSP_AFIFO_EMPTY_SHFT; in HAL_TSP_FIFO_Empty()
4526 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_AFIFOB_EMPTY) >> TSP_AFIFOB_EMPTY_SHFT; in HAL_TSP_FIFO_Empty()
4544 …REG16_W(&_RegCtrl->VQ0_CTRL, (REG16_R(&_RegCtrl->VQ0_CTRL) & (~TSP_VQ0_WR_THRESHOLD_MASK)) | ((0x8… in _HAL_TSP_VQ_TxConfig()
4545 …REG16_W(&_RegCtrl->VQ0_CTRL, (REG16_R(&_RegCtrl->VQ0_CTRL) & (~TSP_VQ0_FORCE_FIRE_CNT_1K_MASK)) | … in _HAL_TSP_VQ_TxConfig()
4548 …REG16_W(&_RegCtrl->VQ1_Config, (REG16_R(&_RegCtrl->VQ1_Config) & (~TSP_VQ1_WR_THRESHOLD_MASK)) | (… in _HAL_TSP_VQ_TxConfig()
4549 …REG16_W(&_RegCtrl->VQ1_Config, (REG16_R(&_RegCtrl->VQ1_Config) & (~TSP_VQ1_FORCEFIRE_CNT_1K_MASK))… in _HAL_TSP_VQ_TxConfig()
4552 …REG16_W(&_RegCtrl->VQ2_Config, (REG16_R(&_RegCtrl->VQ2_Config) & (~TSP_VQ2_WR_THRESHOLD_MASK)) | (… in _HAL_TSP_VQ_TxConfig()
4553 …REG16_W(&_RegCtrl->VQ2_Config, (REG16_R(&_RegCtrl->VQ2_Config) & (~TSP_VQ2_FORCEFIRE_CNT_1K_MASK))… in _HAL_TSP_VQ_TxConfig()
4556 …REG16_W(&_RegCtrl->VQ3_Config, (REG16_R(&_RegCtrl->VQ3_Config) & (~TSP_VQ3_WR_THRESHOLD_MASK)) | (… in _HAL_TSP_VQ_TxConfig()
4557 …REG16_W(&_RegCtrl->VQ3_Config, (REG16_R(&_RegCtrl->VQ3_Config) & (~TSP_VQ3_FORCEFIRE_CNT_1K_MASK))… in _HAL_TSP_VQ_TxConfig()
4605 REG32_W(&_RegCtrl->VQ0_BASE, (u32BaseAddr >> MIU_BUS)); in HAL_TSP_VQ_Buffer()
4606 REG16_W(&_RegCtrl->VQ0_SIZE, u32VQ_PktNum); in HAL_TSP_VQ_Buffer()
4609 REG32_W(&_RegCtrl->VQ1_Base, (u32BaseAddr >> MIU_BUS)); in HAL_TSP_VQ_Buffer()
4610 REG16_W(&_RegCtrl->VQ1_Size, u32VQ_PktNum); in HAL_TSP_VQ_Buffer()
4613 REG32_W(&_RegCtrl->VQ2_Base, (u32BaseAddr >> MIU_BUS)); in HAL_TSP_VQ_Buffer()
4614 REG16_W(&_RegCtrl->VQ2_Size, u32VQ_PktNum); in HAL_TSP_VQ_Buffer()
4617 REG32_W(&_RegCtrl->VQ3_Base, (u32BaseAddr >> MIU_BUS)); in HAL_TSP_VQ_Buffer()
4618 REG16_W(&_RegCtrl->VQ3_Size, u32VQ_PktNum); in HAL_TSP_VQ_Buffer()
4633 REG16_SET(&_RegCtrl->reg160E, TSP_VQTX0_BLOCK_DIS); in HAL_TSP_VQ_Block_Dis()
4636 REG16_SET(&_RegCtrl->reg160E, TSP_VQTX1_BLOCK_DIS); in HAL_TSP_VQ_Block_Dis()
4639 REG16_SET(&_RegCtrl->reg160E, TSP_VQTX2_BLOCK_DIS); in HAL_TSP_VQ_Block_Dis()
4642 REG16_SET(&_RegCtrl->reg160E, TSP_VQTX3_BLOCK_DIS); in HAL_TSP_VQ_Block_Dis()
4653 REG16_CLR(&_RegCtrl->reg160E, TSP_VQTX0_BLOCK_DIS); in HAL_TSP_VQ_Block_Dis()
4656 REG16_CLR(&_RegCtrl->reg160E, TSP_VQTX1_BLOCK_DIS); in HAL_TSP_VQ_Block_Dis()
4659 REG16_CLR(&_RegCtrl->reg160E, TSP_VQTX2_BLOCK_DIS); in HAL_TSP_VQ_Block_Dis()
4662 REG16_CLR(&_RegCtrl->reg160E, TSP_VQTX3_BLOCK_DIS); in HAL_TSP_VQ_Block_Dis()
4676 REG16_SET(&_RegCtrl->HW2_Config3, TSP_VQ_EN|TSP_VQ2PINGPONG_EN); in HAL_TSP_VQ_Enable()
4680 REG16_CLR(&_RegCtrl->HW2_Config3, TSP_VQ_EN|TSP_VQ2PINGPONG_EN); in HAL_TSP_VQ_Enable()
4690 REG16_SET(&_RegCtrl->VQ0_CTRL, TSP_VQ0_RESET); in HAL_TSP_VQ_Reset()
4693 REG16_SET(&_RegCtrl->VQ1_Config, TSP_VQ1_RESET); in HAL_TSP_VQ_Reset()
4696 REG16_SET(&_RegCtrl->VQ2_Config, TSP_VQ2_RESET); in HAL_TSP_VQ_Reset()
4699 REG16_SET(&_RegCtrl->VQ3_Config, TSP_VQ3_RESET); in HAL_TSP_VQ_Reset()
4710 REG16_CLR(&_RegCtrl->VQ0_CTRL, TSP_VQ0_RESET); in HAL_TSP_VQ_Reset()
4713 REG16_CLR(&_RegCtrl->VQ1_Config, TSP_VQ1_RESET); in HAL_TSP_VQ_Reset()
4716 REG16_CLR(&_RegCtrl->VQ2_Config, TSP_VQ2_RESET); in HAL_TSP_VQ_Reset()
4719 REG16_CLR(&_RegCtrl->VQ3_Config, TSP_VQ3_RESET); in HAL_TSP_VQ_Reset()
4734 REG16_SET(&_RegCtrl->VQ0_CTRL, TSP_VQ0_OVERFLOW_INT_EN); in HAL_TSP_VQ_OverflowInt_En()
4737 REG16_SET(&_RegCtrl->VQ1_Config, TSP_VQ1_OVF_INT_EN); in HAL_TSP_VQ_OverflowInt_En()
4740 REG16_SET(&_RegCtrl->VQ2_Config, TSP_VQ2_OVF_INT_EN); in HAL_TSP_VQ_OverflowInt_En()
4743 REG16_SET(&_RegCtrl->VQ3_Config, TSP_VQ3_OVF_INT_EN); in HAL_TSP_VQ_OverflowInt_En()
4754 REG16_CLR(&_RegCtrl->VQ0_CTRL, TSP_VQ0_OVERFLOW_INT_EN); in HAL_TSP_VQ_OverflowInt_En()
4757 REG16_CLR(&_RegCtrl->VQ1_Config, TSP_VQ1_OVF_INT_EN); in HAL_TSP_VQ_OverflowInt_En()
4760 REG16_CLR(&_RegCtrl->VQ2_Config, TSP_VQ2_OVF_INT_EN); in HAL_TSP_VQ_OverflowInt_En()
4763 REG16_CLR(&_RegCtrl->VQ3_Config, TSP_VQ3_OVF_INT_EN); in HAL_TSP_VQ_OverflowInt_En()
4778 REG16_SET(&_RegCtrl->VQ0_CTRL, TSP_VQ0_CLR_OVERFLOW_INT); in HAL_TSP_VQ_OverflowInt_Clr()
4781 REG16_SET(&_RegCtrl->VQ1_Config, TSP_VQ1_CLR_OVF_INT); in HAL_TSP_VQ_OverflowInt_Clr()
4784 REG16_SET(&_RegCtrl->VQ2_Config, TSP_VQ2_CLR_OVF_INT); in HAL_TSP_VQ_OverflowInt_Clr()
4787 REG16_SET(&_RegCtrl->VQ3_Config, TSP_VQ3_CLR_OVF_INT); in HAL_TSP_VQ_OverflowInt_Clr()
4798 REG16_CLR(&_RegCtrl->VQ0_CTRL, TSP_VQ0_CLR_OVERFLOW_INT); in HAL_TSP_VQ_OverflowInt_Clr()
4801 REG16_CLR(&_RegCtrl->VQ1_Config, TSP_VQ1_CLR_OVF_INT); in HAL_TSP_VQ_OverflowInt_Clr()
4804 REG16_CLR(&_RegCtrl->VQ2_Config, TSP_VQ2_CLR_OVF_INT); in HAL_TSP_VQ_OverflowInt_Clr()
4807 REG16_CLR(&_RegCtrl->VQ3_Config, TSP_VQ3_CLR_OVF_INT); in HAL_TSP_VQ_OverflowInt_Clr()
4821 REG16_SET(&(_RegCtrl->reg15b8), TSP_PVR1_PINGPONG); in HAL_PVR_Init()
4822 …REG16_W(&(_RegCtrl->FIFO_Src), (REG16_R(&(_RegCtrl->FIFO_Src)) & ~TSP_PVR1_SRC_MASK) | (((MS_U16)p… in HAL_PVR_Init()
4826 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_REG_PINGPONG_EN); in HAL_PVR_Init()
4827 …REG16_W(&(_RegCtrl->FIFO_Src), (REG16_R(&(_RegCtrl->FIFO_Src)) & ~TSP_PVR2_SRC_MASK_L) | ((((MS_U1… in HAL_PVR_Init()
4828 …REG16_W(&(_RegCtrl->PCR_Cfg), (REG16_R(&(_RegCtrl->PCR_Cfg)) & ~TSP_PVR2_SRC_MASK_H) | ((((MS_U16)… in HAL_PVR_Init()
4851 REG16_CLR(&(_RegCtrl->reg15b8), TSP_PVR1_PINGPONG); in HAL_PVR_Exit()
4852 REG16_CLR(&(_RegCtrl->FIFO_Src), TSP_PVR1_SRC_MASK); in HAL_PVR_Exit()
4855 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH); in HAL_PVR_Exit()
4856 REG16_CLR(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH); in HAL_PVR_Exit()
4860 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_REG_PINGPONG_EN); in HAL_PVR_Exit()
4861 REG16_CLR(&(_RegCtrl->FIFO_Src), TSP_PVR2_SRC_MASK_L); in HAL_PVR_Exit()
4862 REG16_CLR(&(_RegCtrl->PCR_Cfg), TSP_PVR2_SRC_MASK_H); in HAL_PVR_Exit()
4865 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR); in HAL_PVR_Exit()
4866 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR); in HAL_PVR_Exit()
4901 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH); in HAL_PVR_Start()
4902 REG16_CLR(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH); in HAL_PVR_Start()
4905 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_ENABLE); in HAL_PVR_Start()
4909 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR); in HAL_PVR_Start()
4910 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR); in HAL_PVR_Start()
4913 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_EN); in HAL_PVR_Start()
4941 REG16_CLR(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_ENABLE); in HAL_PVR_Stop()
4944 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_EN); in HAL_PVR_Stop()
4966 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_PAUSE); in HAL_PVR_Pause()
4969 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_PAUSE); in HAL_PVR_Pause()
4986 REG16_CLR(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_PAUSE); in HAL_PVR_Pause()
4989 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_PAUSE); in HAL_PVR_Pause()
5010 REG16_SET(&(_RegCtrl->reg15b4), TSP_PVR_PID_BYPASS); in HAL_PVR_RecPid()
5011 REG16_CLR(&(_RegCtrl->PVRConfig), TSP_PVR1_REC_ALL_EN); in HAL_PVR_RecPid()
5014 REG16_SET(&(_RegCtrl->reg15b4), TSP_PVR_PID_BYPASS2); in HAL_PVR_RecPid()
5015 REG16_CLR(&(_RegCtrl->PVRConfig), TSP_PVR2_REC_ALL_EN); in HAL_PVR_RecPid()
5034 REG16_CLR(&(_RegCtrl->reg15b4), TSP_PVR_PID_BYPASS); in HAL_PVR_RecPid()
5035 REG16_SET(&(_RegCtrl->PVRConfig), TSP_PVR1_REC_ALL_EN); in HAL_PVR_RecPid()
5038 REG16_CLR(&(_RegCtrl->reg15b4), TSP_PVR_PID_BYPASS2); in HAL_PVR_RecPid()
5039 REG16_SET(&(_RegCtrl->PVRConfig), TSP_PVR2_REC_ALL_EN); in HAL_PVR_RecPid()
5059 REG16_SET(&(_RegCtrl->PVRConfig), TSP_REC_NULL); in HAL_PVR_RecNull()
5063 REG16_CLR(&(_RegCtrl->PVRConfig), TSP_REC_NULL); in HAL_PVR_RecNull()
5085 … REG32_W(&_RegCtrl->TsRec_Head, (phyMiuOffsetPvrBuf0 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
5087 REG32_W(&(_RegCtrl->TsRec_Tail), (u32EndAddr0 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
5089 …REG32_W(&(_RegCtrl->TsRec_Mid_PVR1_WPTR), (phyMiuOffsetPvrBuf0 >>MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
5092 …REG32_W(&_RegCtrl->Str2mi_head2pvr1, (phyMiuOffsetPvrBuf1>> MIU_BUS) & TSP_HW_PVR1_BUF_HEAD2_MASK); in HAL_PVR_SetBuf()
5094 … REG32_W(&(_RegCtrl->Str2mi_tail2pvr1), (u32EndAddr1 >> MIU_BUS) &TSP_HW_PVR1_BUF_TAIL2_MASK); in HAL_PVR_SetBuf()
5096 … REG32_W(&(_RegCtrl->Str2mi_mid2pvr1), (phyMiuOffsetPvrBuf1>>MIU_BUS) & TSP_HW_PVR1_BUF_MID2_MASK); in HAL_PVR_SetBuf()
5103 … REG32_W(&_RegCtrl->Str2mi_head1_pvr2, (phyMiuOffsetPvrBuf0 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
5105 REG32_W(&_RegCtrl->Str2mi_tail1_pvr2, (u32EndAddr0>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
5107 …REG32_W(&(_RegCtrl->Str2mi_mid1_wptr_pvr2), (phyMiuOffsetPvrBuf0 >>MIU_BUS) & TSP_STR2MI2_ADDR_MAS… in HAL_PVR_SetBuf()
5110 … REG32_W(&_RegCtrl->Str2mi_head2_pvr2, (phyMiuOffsetPvrBuf1 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
5112 REG32_W(&_RegCtrl->Str2mi_tail2_pvr2, (u32EndAddr1 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
5114 … REG32_W(&(_RegCtrl->Str2mi_mid2_pvr2), (phyMiuOffsetPvrBuf1 >>MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
5165 REG32_W(&_RegCtrl->TsRec_Head, (u32StartAddr0>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_StartAddr()
5168 … REG32_W(&_RegCtrl->Str2mi_head2pvr1, (u32StartAddr1>> MIU_BUS) & TSP_HW_PVR1_BUF_HEAD2_MASK); in HAL_PVR_SetStr2Miu_StartAddr()
5172 … REG32_W(&_RegCtrl->Str2mi_head1_pvr2, (u32StartAddr0>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_StartAddr()
5175 … REG32_W(&_RegCtrl->Str2mi_head2_pvr2, (u32StartAddr1>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_StartAddr()
5203 REG32_W(&(_RegCtrl->TsRec_Mid_PVR1_WPTR), (u32MidAddr0>>4) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_MidAddr()
5206 REG32_W(&(_RegCtrl->Str2mi_mid2pvr1), (u32MidAddr1>>4) & TSP_HW_PVR1_BUF_MID2_MASK); in HAL_PVR_SetStr2Miu_MidAddr()
5210 REG32_W(&(_RegCtrl->Str2mi_mid1_wptr_pvr2), (u32MidAddr0>>4) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_MidAddr()
5213 REG32_W(&(_RegCtrl->Str2mi_mid2_pvr2), (u32MidAddr1>>4) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_MidAddr()
5240 REG32_W(&(_RegCtrl->TsRec_Tail), (u32EndAddr0 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_EndAddr()
5243 … REG32_W(&(_RegCtrl->Str2mi_tail2pvr1), (u32EndAddr1 >> MIU_BUS) &TSP_HW_PVR1_BUF_TAIL2_MASK); in HAL_PVR_SetStr2Miu_EndAddr()
5247 REG32_W(&_RegCtrl->Str2mi_tail1_pvr2, (u32EndAddr0>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_EndAddr()
5250 REG32_W(&_RegCtrl->Str2mi_tail2_pvr2, (u32EndAddr1>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_EndAddr()
5276 return (REG32_R(&_RegCtrl->TsRec_Mid_PVR1_WPTR) << MIU_BUS); in HAL_PVR_GetWritePtr()
5279 return (REG32_R(&_RegCtrl->Str2mi_mid1_wptr_pvr2) << MIU_BUS); in HAL_PVR_GetWritePtr()
5302 *eSrc = ((REG16_R(&(_RegCtrl->FIFO_Src)) & TSP_PVR1_SRC_MASK) >> TSP_PVR1_SRC_SHIFT); in HAL_PVR_GetEngSrc()
5306 … u16Value = (REG16_R(&(_RegCtrl->FIFO_Src)) & TSP_PVR2_SRC_MASK_L) >> TSP_PVR2_SRC_SHIFT_L; in HAL_PVR_GetEngSrc()
5307 u16Value |= ((REG16_R(&(_RegCtrl->PCR_Cfg)) & TSP_PVR2_SRC_MASK_H) << 1); in HAL_PVR_GetEngSrc()
5554 REG16_SET(&_RegCtrl->reg160C, TSP_RECORD192_EN); in HAL_PVR_SetStrPacketMode()
5557 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_PKT192_EN); in HAL_PVR_SetStrPacketMode()
5574 REG16_CLR(&_RegCtrl->reg160C, TSP_RECORD192_EN); in HAL_PVR_SetStrPacketMode()
5577 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_PKT192_EN); in HAL_PVR_SetStrPacketMode()
5597 REG16_CLR(&_RegCtrl->reg160C, TSP_PVR1_LPCR1_RLD); in HAL_PVR_GetPVRTimeStamp()
5599 u32lpcr = REG32_R(&_RegCtrl->PVR1_LPcr1); in HAL_PVR_GetPVRTimeStamp()
5601 REG16_SET(&_RegCtrl->reg160C, TSP_PVR1_LPCR1_RLD); in HAL_PVR_GetPVRTimeStamp()
5605 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_RLD); in HAL_PVR_GetPVRTimeStamp()
5607 u32lpcr = REG32_R(&_RegCtrl->PVR2_LPCR1); in HAL_PVR_GetPVRTimeStamp()
5609 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_RLD); in HAL_PVR_GetPVRTimeStamp()
5636 REG16_SET(&_RegCtrl->reg160C, TSP_PVR1_LPCR1_WLD); in HAL_PVR_SetPVRTimeStamp()
5638 REG32_W(&_RegCtrl->PVR1_LPcr1, u32Stamp); in HAL_PVR_SetPVRTimeStamp()
5640 REG16_CLR(&_RegCtrl->reg160C, TSP_PVR1_LPCR1_WLD); in HAL_PVR_SetPVRTimeStamp()
5643 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_WLD); in HAL_PVR_SetPVRTimeStamp()
5645 REG32_W(&_RegCtrl->PVR2_LPCR1, u32Stamp); in HAL_PVR_SetPVRTimeStamp()
5647 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_WLD); in HAL_PVR_SetPVRTimeStamp()
5712 REG16_SET(&_RegCtrl->HW2_Config3, TSP_PVR1_ALIGN_EN); in HAL_PVR_Alignment_Enable()
5715 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_PVR_ALIGN_EN); in HAL_PVR_Alignment_Enable()
5732 REG16_CLR(&_RegCtrl->HW2_Config3, TSP_PVR1_ALIGN_EN); in HAL_PVR_Alignment_Enable()
5735 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_PVR_ALIGN_EN); in HAL_PVR_Alignment_Enable()
5826 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR1_BLOCK_DIS); in HAL_PVR_Block_Dis()
5829 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_BLOCK_DIS); in HAL_PVR_Block_Dis()
5846 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR1_BLOCK_DIS); in HAL_PVR_Block_Dis()
5849 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_BLOCK_DIS); in HAL_PVR_Block_Dis()
5869 … REG16_MSK_W(&_RegCtrl->reg15b8, TSP_BURST_LEN_MASK, (u16BurstMode << TSP_BURST_LEN_SHIFT)); in HAL_PVR_BurstLen()
5872 …REG32_MSK_W(&_RegCtrl->PVR2_Config, TSP_PVR2_BURST_LEN_MASK, (u16BurstMode << TSP_PVR2_BURST_LEN_S… in HAL_PVR_BurstLen()
5984 REG16_W(&_RegCtrl->MOBF_PVR1_Index[0], (u32Key & TSP_MOBF_PVR1_INDEX_MASK)); in HAL_PVR_MOBF_Enable()
5987 REG16_W(&_RegCtrl->MOBF_PVR2_Index[0], (u32Key & TSP_MOBF_PVR2_INDEX_MASK)); in HAL_PVR_MOBF_Enable()
6065 REG32_W(&_RegCtrl->MCU_Data0, INFO_FW_VERSION); in HAL_TSP_HCMD_GetInfo()
6068 REG32_W(&_RegCtrl->MCU_Data0, INFO_FW_DATE); in HAL_TSP_HCMD_GetInfo()
6071 REG32_W(&_RegCtrl->MCU_Data0, INFO_FW_VERSION); in HAL_TSP_HCMD_GetInfo()
6076 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_INFO); in HAL_TSP_HCMD_GetInfo()
6079 u32Data = REG32_R(&_RegCtrl->MCU_Data1); in HAL_TSP_HCMD_GetInfo()
6080 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear in HAL_TSP_HCMD_GetInfo()
6089 REG32_W(&_RegCtrl->MCU_Data0 , u32Value); in HAL_TSP_HCMD_BufRst()
6090 REG32_W(&_RegCtrl->MCU_Cmd , TSP_MCU_CMD_BUFRST); in HAL_TSP_HCMD_BufRst()
6100 REG32_W(&_RegCtrl->MCU_Data0, u32Addr); in HAL_TSP_HCMD_Read()
6101 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_READ); in HAL_TSP_HCMD_Read()
6104 u32Data = REG32_R(&_RegCtrl->MCU_Data1); in HAL_TSP_HCMD_Read()
6105 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear in HAL_TSP_HCMD_Read()
6115 REG32_W(&_RegCtrl->MCU_Data0, u32Addr); in HAL_TSP_HCMD_Write()
6116 REG32_W(&_RegCtrl->MCU_Data1, u32Value); in HAL_TSP_HCMD_Write()
6117 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_WRITE); in HAL_TSP_HCMD_Write()
6120 u32Data = REG32_R(&_RegCtrl->MCU_Data1); in HAL_TSP_HCMD_Write()
6121 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear in HAL_TSP_HCMD_Write()
6131 REG32_W(&_RegCtrl->MCU_Data1, 0); in HAL_TSP_HCMD_Alive()
6132 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_ALIVE); //@TODO check FW HCMD in HAL_TSP_HCMD_Alive()
6134 u32Data = REG32_R(&_RegCtrl->MCU_Data1); in HAL_TSP_HCMD_Alive()
6135 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear in HAL_TSP_HCMD_Alive()
6142 REG32_W(&_RegCtrl->MCU_Data0, mcu_data0); in HAL_TSP_HCMD_SET()
6143 REG32_W(&_RegCtrl->MCU_Data1, mcu_data1); in HAL_TSP_HCMD_SET()
6144 REG32_W(&_RegCtrl->MCU_Cmd, mcu_cmd); in HAL_TSP_HCMD_SET()
6149 *pmcu_cmd = REG32_R(&_RegCtrl->MCU_Cmd); in HAL_TSP_HCMD_GET()
6150 *pmcu_data0 = REG32_R(&_RegCtrl->MCU_Data0); in HAL_TSP_HCMD_GET()
6151 *pmcu_data1 = REG32_R(&_RegCtrl->MCU_Data1); in HAL_TSP_HCMD_GET()
6158 REG32_W(&_RegCtrl->MCU_Data0, FltId); in HAL_TSP_HCMD_SecRdyInt_Disable()
6159 REG32_W(&_RegCtrl->MCU_Data1,u32Data); in HAL_TSP_HCMD_SecRdyInt_Disable()
6160 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_SECRDYINT_DISABLE); // @TODO add HCMD list here in HAL_TSP_HCMD_SecRdyInt_Disable()
6162 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear in HAL_TSP_HCMD_SecRdyInt_Disable()
6171 REG32_W(&_RegCtrl->MCU_Data0, u32Enable); in HAL_TSP_HCMD_Dbg()
6172 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_DBG); in HAL_TSP_HCMD_Dbg()
6175 u32Data = REG32_R(&_RegCtrl->MCU_Data1); in HAL_TSP_HCMD_Dbg()
6176 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear in HAL_TSP_HCMD_Dbg()
6178 return REG32_R(&_RegCtrl->MCU_Data1); in HAL_TSP_HCMD_Dbg()
6183 REG16_CLR(&_RegCtrl->DBG_SEL, TSP_DBG_SEL_MASK); in HAL_TSP_GetDBGStatus()
6184 REG16_SET(&_RegCtrl->DBG_SEL, ((u16Sel << TSP_DBG_SEL_SHIFT) & TSP_DBG_SEL_MASK)); in HAL_TSP_GetDBGStatus()
6186 return REG32_R(&_RegCtrl->TSP_Debug); in HAL_TSP_GetDBGStatus()
6203 REG16_SET(&_RegCtrl->HwInt_Stat, (TSP_HWINT_EN_MASK & u32Mask) | TSP_HWINT_STATUS_MASK); in HAL_TSP_INT_Enable()
6216 … REG16_SET(&_RegCtrl->HwInt2_Stat, (TSP_HWINT2_EN_MASK & (u32Mask >> 8)) | TSP_HWINT2_STATUS_MASK); in HAL_TSP_INT_Enable()
6224 …REG16_SET(&_RegCtrl->HwInt3_Stat, (TSP_HWINT3_EN_MASK & (u32Mask >> 16)) | TSP_HWINT3_STATUS_MASK); in HAL_TSP_INT_Enable()
6234 REG16_W(&_RegCtrl->HwInt_Stat, in HAL_TSP_INT_Disable()
6235 … (REG16_R(&_RegCtrl->HwInt_Stat) & ~(TSP_HWINT_EN_MASK & (u32Mask))) | TSP_HWINT_STATUS_MASK); in HAL_TSP_INT_Disable()
6237 REG16_W(&_RegCtrl->HwInt2_Stat, in HAL_TSP_INT_Disable()
6238 …(REG16_R(&_RegCtrl->HwInt2_Stat) & ~(TSP_HWINT2_EN_MASK & (u32Mask >> 8))) | TSP_HWINT2_STATUS_MAS… in HAL_TSP_INT_Disable()
6240 REG16_W(&_RegCtrl->HwInt3_Stat, in HAL_TSP_INT_Disable()
6241 …(REG16_R(&_RegCtrl->HwInt3_Stat) & ~(TSP_HWINT3_EN_MASK & (u32Mask >> 16))) | TSP_HWINT3_STATUS_MA… in HAL_TSP_INT_Disable()
6251 REG16_W(&_RegCtrl->HwInt_Stat, in HAL_TSP_INT_ClrHW()
6252 (REG16_R(&_RegCtrl->HwInt_Stat) & (~TSP_HWINT_STATUS_MASK)) | in HAL_TSP_INT_ClrHW()
6255 REG16_W(&_RegCtrl->HwInt2_Stat, in HAL_TSP_INT_ClrHW()
6256 (REG16_R(&_RegCtrl->HwInt2_Stat) & (~TSP_HWINT2_STATUS_MASK)) | in HAL_TSP_INT_ClrHW()
6259 REG16_W(&_RegCtrl->HwInt3_Stat, in HAL_TSP_INT_ClrHW()
6260 (REG16_R(&_RegCtrl->HwInt3_Stat) & (~TSP_HWINT3_STATUS_MASK)) | in HAL_TSP_INT_ClrHW()
6269 …status = (MS_U32)(((REG16_R(&_RegCtrl->HwInt3_Stat) & TSP_HWINT3_STATUS_MASK) >> TSP_HWINT3_STATUS… in HAL_TSP_INT_GetHW()
6272 …status |= ((MS_U32)(((REG16_R(&_RegCtrl->HwInt2_Stat) & TSP_HWINT2_STATUS_MASK) >> TSP_HWINT2_STAT… in HAL_TSP_INT_GetHW()
6275 …status |= ((MS_U32)((REG16_R(&_RegCtrl->HwInt_Stat) & TSP_HWINT_STATUS_MASK) >> TSP_HWINT_STATUS_S… in HAL_TSP_INT_GetHW()
6282 REG32_W(&_RegCtrl->SwInt_Stat, 0); in HAL_TSP_INT_ClrSW()
6287 return REG32_R(&_RegCtrl->SwInt_Stat); in HAL_TSP_INT_GetSW()
6578 REG16_SET(&_RegCtrl->reg15b8, TSP_REMOVE_DUP_AV_PKT); in HAL_TSP_PktDmx_RmDupAVPkt()
6582 REG16_CLR(&_RegCtrl->reg15b8, TSP_REMOVE_DUP_AV_PKT); in HAL_TSP_PktDmx_RmDupAVPkt()
6593 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_APES_ERR_RM_EN); in HAL_TSP_TEI_RemoveErrorPkt()
6596 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_VPES_ERR_RM_EN); in HAL_TSP_TEI_RemoveErrorPkt()
6607 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_APES_ERR_RM_EN); in HAL_TSP_TEI_RemoveErrorPkt()
6610 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_VPES_ERR_RM_EN); in HAL_TSP_TEI_RemoveErrorPkt()
6625 REG16_SET(&_RegCtrl->reg15b8, TSP_TEI_SKIPE_PKT_PID0); in HAL_TSP_TEI_SKIP()
6628 REG16_SET(&_RegCtrl->reg15b8, TSP_TEI_SKIPE_PKT_PID1); in HAL_TSP_TEI_SKIP()
6631 REG32_SET(&_RegCtrl->PVR2_Config, TSP_TEI_SKIP_PKT2); in HAL_TSP_TEI_SKIP()
6634 REG16_SET(&_RegCtrl->reg15b8, TSP_TEI_SKIPE_PKT_PID3); in HAL_TSP_TEI_SKIP()
6645 REG16_CLR(&_RegCtrl->reg15b8, TSP_TEI_SKIPE_PKT_PID0); in HAL_TSP_TEI_SKIP()
6648 REG16_CLR(&_RegCtrl->reg15b8, TSP_TEI_SKIPE_PKT_PID1); in HAL_TSP_TEI_SKIP()
6651 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_TEI_SKIP_PKT2); in HAL_TSP_TEI_SKIP()
6654 REG16_CLR(&_RegCtrl->reg15b8, TSP_TEI_SKIPE_PKT_PID3); in HAL_TSP_TEI_SKIP()
6713 REG16_SET(&_RegCtrl->reg160C,TSP_ORZ_DMAW_PROT_EN); in HAL_TSP_OR_Address_Protect_En()
6717 REG16_CLR(&_RegCtrl->reg160C,TSP_ORZ_DMAW_PROT_EN); in HAL_TSP_OR_Address_Protect_En()
6729 … REG32_W(&_RegCtrl->ORZ_DMAW_LBND,(MS_U32)((phyMiuOffsetLB >> MIU_BUS) & TSP_ORZ_DMAW_LBND_MASK)); in HAL_TSP_OR_Address_Protect()
6730 … REG32_W(&_RegCtrl->ORZ_DMAW_UBND,(MS_U32)((phyMiuOffsetUB >> MIU_BUS) & TSP_ORZ_DMAW_UBND_MASK)); in HAL_TSP_OR_Address_Protect()
6739 REG16_SET(&_RegCtrl->reg15b4,TSP_SEC_CB_PVR2_DAMW_PROTECT_EN); in HAL_TSP_SEC_Address_Protect_En()
6743 REG16_CLR(&_RegCtrl->reg15b4,TSP_SEC_CB_PVR2_DAMW_PROTECT_EN); in HAL_TSP_SEC_Address_Protect_En()
6761 REG32_W(&_RegCtrl->DMAW_LBND0,u32LBnd); in HAL_TSP_SEC_Address_Protect()
6762 REG32_W(&_RegCtrl->DMAW_UBND0,u32UBnd); in HAL_TSP_SEC_Address_Protect()
6765 REG32_W(&_RegCtrl->DMAW_LBND1,u32LBnd); in HAL_TSP_SEC_Address_Protect()
6766 REG32_W(&_RegCtrl->DMAW_UBND1,u32UBnd); in HAL_TSP_SEC_Address_Protect()
6832 REG32_W(&_RegCtrl->DMAW_LBND2, u32LBnd); in HAL_TSP_PVR_Address_Protect()
6833 REG32_W(&_RegCtrl->DMAW_UBND2, u32UBnd); in HAL_TSP_PVR_Address_Protect()
6836 REG32_W(&_RegCtrl->DMAW_LBND3, u32LBnd); in HAL_TSP_PVR_Address_Protect()
6837 REG32_W(&_RegCtrl->DMAW_UBND3, u32UBnd); in HAL_TSP_PVR_Address_Protect()
6840 REG32_W(&_RegCtrl->DMAW_LBND4, u32LBnd); in HAL_TSP_PVR_Address_Protect()
6841 REG32_W(&_RegCtrl->DMAW_UBND4, u32UBnd); in HAL_TSP_PVR_Address_Protect()
7027 REG32_W(&_RegCtrl->MCU_Data1, u32Config0); in HAL_TSP_CMD_Run()
7028 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_SEC_CC_CHECK_DISABLE); in HAL_TSP_CMD_Run()
7030 u32Data = REG32_R(&_RegCtrl->MCU_Data1); in HAL_TSP_CMD_Run()
7031 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear in HAL_TSP_CMD_Run()
7218 u16PktDmxSrc = _CLR_(REG16_R(&_RegCtrl->reg15b8), TSP_MATCH_PID_SRC_MASK); in HAL_DSCMB_GetStatus()
7238 REG16_W(&_RegCtrl->reg15b8, u16PktDmxSrc); in HAL_DSCMB_GetStatus()
7240 …REG16_W(&_RegCtrl->PVRConfig, _SET_(REG16_R(&_RegCtrl->PVRConfig), TSP_MATCH_PID_LD)); // Set 1 to… in HAL_DSCMB_GetStatus()
7243 REG16_W(&_RegCtrl->PVRConfig, _CLR_(REG16_R(&_RegCtrl->PVRConfig), TSP_MATCH_PID_LD)); // freeze in HAL_DSCMB_GetStatus()
7245 u16WordId = _CLR_(REG16_R(&_RegCtrl->PVRConfig), TSP_MATCH_PID_SEL_MASK); in HAL_DSCMB_GetStatus()
7250 REG16_MSK_W(&_RegCtrl->PVRConfig,TSP_MATCH_PID_SEL_MASK,u16WordId); in HAL_DSCMB_GetStatus()
7257 *pu32ScmbSts = _AND_(REG32_R(&_RegCtrl->TsPidScmbStatTsin), u32PIDFltMask); in HAL_DSCMB_GetStatus()
7259 …REG16_W(&_RegCtrl->PVRConfig, _SET_(REG16_R(&_RegCtrl->PVRConfig), TSP_MATCH_PID_LD)); // re-enable in HAL_DSCMB_GetStatus()