Lines Matching refs:REG32_CLR
121 #define REG32_CLR(reg, value) REG32_W(reg, _CLR_(REG32_R(reg), value)) macro
899 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_TS_IF2_EN); in HAL_TSP_TSIF_LiveEn()
1658 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_TS_DATA2_SWAP); in HAL_TSP_TSIF_BitSwap()
1706 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_EXT_SYNC_SEL2); in HAL_TSP_TSIF_ExtSync()
1846 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_P_SEL2); in HAL_TSP_TSIF_Parl()
4388 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_V_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4391 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_V3d_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4394 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_A_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4397 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_AD_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4400 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_AC_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4403 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_ADD_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
4860 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_REG_PINGPONG_EN); in HAL_PVR_Exit()
4866 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR); in HAL_PVR_Exit()
4910 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR); in HAL_PVR_Start()
4944 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_EN); in HAL_PVR_Stop()
4989 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_PAUSE); in HAL_PVR_Pause()
5577 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_PKT192_EN); in HAL_PVR_SetStrPacketMode()
5605 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_RLD); in HAL_PVR_GetPVRTimeStamp()
5647 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_WLD); in HAL_PVR_SetPVRTimeStamp()
5735 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_PVR_ALIGN_EN); in HAL_PVR_Alignment_Enable()
5846 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR1_BLOCK_DIS); in HAL_PVR_Block_Dis()
5849 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_BLOCK_DIS); in HAL_PVR_Block_Dis()
6651 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_TEI_SKIP_PKT2); in HAL_TSP_TEI_SKIP()