Lines Matching refs:CFG_16
273 REG16_SET(&_RegCtrl2->CFG_16, CFG_16_PID_BYPASS3_REC); in HAL_TSP_HwPatch()
279 REG16_SET((&_RegCtrl2->CFG_16), CFG_16_PVR3_LPCR1_RLD); in HAL_TSP_HwPatch()
4833 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PVR3_REG_PINGPONG_EN); in HAL_PVR_Init()
4871 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_PVR3_REG_PINGPONG_EN); in HAL_PVR_Exit()
4874 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_RST_WADR); in HAL_PVR_Exit()
4875 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_RST_WADR); in HAL_PVR_Exit()
4917 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_RST_WADR); in HAL_PVR_Start()
4918 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_RST_WADR); in HAL_PVR_Start()
4921 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_EN); in HAL_PVR_Start()
4948 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_EN); in HAL_PVR_Stop()
4972 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_PAUSE); in HAL_PVR_Pause()
4992 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_PAUSE); in HAL_PVR_Pause()
5018 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PID_BYPASS3_REC); in HAL_PVR_RecPid()
5019 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_REC_ALL3); in HAL_PVR_RecPid()
5042 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_PID_BYPASS3_REC); in HAL_PVR_RecPid()
5043 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_REC_ALL3); in HAL_PVR_RecPid()
5560 REG16_SET((&_RegCtrl2->CFG_16), CFG_16_PVR3_PKT192_EN); in HAL_PVR_SetStrPacketMode()
5580 REG16_CLR((&_RegCtrl2->CFG_16), CFG_16_PVR3_PKT192_EN); in HAL_PVR_SetStrPacketMode()
5612 REG16_CLR((&_RegCtrl2->CFG_16), CFG_16_PVR3_LPCR1_RLD); in HAL_PVR_GetPVRTimeStamp()
5616 REG16_SET((&_RegCtrl2->CFG_16), CFG_16_PVR3_LPCR1_RLD); in HAL_PVR_GetPVRTimeStamp()
5650 REG16_SET(&_RegCtrl2->CFG_16, CFG_16_PVR3_LPCR1_WLD); in HAL_PVR_SetPVRTimeStamp()
5654 REG16_CLR(&_RegCtrl2->CFG_16, CFG_16_PVR3_LPCR1_WLD); in HAL_PVR_SetPVRTimeStamp()
5718 REG16_SET(&_RegCtrl2->CFG_16, CFG_16_PVR3_PVR_ALIGN_EN); in HAL_PVR_Alignment_Enable()
5738 REG16_CLR(&_RegCtrl2->CFG_16, CFG_16_PVR3_PVR_ALIGN_EN); in HAL_PVR_Alignment_Enable()
5832 REG16_SET(&_RegCtrl2->CFG_16, CFG_16_PVR3_BLOCK_DIS); in HAL_PVR_Block_Dis()
5852 REG16_CLR(&_RegCtrl2->CFG_16, CFG_16_PVR3_BLOCK_DIS); in HAL_PVR_Block_Dis()
5875 …REG16_MSK_W(&_RegCtrl2->CFG_16, CFG_16_PVR3_BURST_LEN_MASK, (u16BurstMode << CFG_16_PVR3_BURST_LEN… in HAL_PVR_BurstLen()