3931 TSP_SRC_SEQ HAL_TSP_Eng2PktDmx_Mapping(MS_U32 u32Eng)  in HAL_TSP_Eng2PktDmx_Mapping()  argument
3933     switch(u32Eng)  in HAL_TSP_Eng2PktDmx_Mapping()
4020 MS_U32 HAL_TSP_PidFltDstMapping(TSP_PIDFLT_DST eDstType, MS_U32 u32Eng)  in HAL_TSP_PidFltDstMapping()  argument
4024         switch(u32Eng)  in HAL_TSP_PidFltDstMapping()
4037         switch(u32Eng)  in HAL_TSP_PidFltDstMapping()
4054         switch(u32Eng)  in HAL_TSP_PidFltDstMapping()
5431 MS_BOOL HAL_TSP_CAPVR_SPSEnable(MS_U32 u32Eng, MS_U16 u16CaPvrMode, MS_BOOL bEnable)  in HAL_TSP_CAPVR_SPSEnable()  argument
5435     switch(u32Eng)  in HAL_TSP_CAPVR_SPSEnable()
5449         switch(u32Eng)  in HAL_TSP_CAPVR_SPSEnable()
5472 void HAL_TSP_PVR_SPSConfig(MS_U32 u32Eng, MS_BOOL CTR_mode)  in HAL_TSP_PVR_SPSConfig()  argument
5474     switch(u32Eng)  in HAL_TSP_PVR_SPSConfig()
5516         printf("SPS CTR mode = %p\n",&(_RegCtrl8[u32Eng].CFG8_05));  in HAL_TSP_PVR_SPSConfig()
5517         REG16_SET(&(_RegCtrl8[u32Eng].CFG8_05),CFG8_05_CTR_MODE_SPS_PVR1);   //set CTR mode  in HAL_TSP_PVR_SPSConfig()
5518         REG16_W(&(_RegCtrl8[u32Eng].CFG8_00_03[0]), 0x0000);                 //set counter IV  in HAL_TSP_PVR_SPSConfig()
5519         REG16_W(&(_RegCtrl8[u32Eng].CFG8_00_03[1]), 0x0000);  in HAL_TSP_PVR_SPSConfig()
5520         REG16_W(&(_RegCtrl8[u32Eng].CFG8_00_03[2]), 0x0000);  in HAL_TSP_PVR_SPSConfig()
5521         REG16_W(&(_RegCtrl8[u32Eng].CFG8_00_03[3]), 0x0000);  in HAL_TSP_PVR_SPSConfig()
5522 …      REG16_W(&(_RegCtrl8[u32Eng].CFG8_04), CFG8_04_CTR_IV_SPS_MAX_1K);    //set counter IV max vld  in HAL_TSP_PVR_SPSConfig()
5523         REG16_SET(&(_RegCtrl8[u32Eng].CFG8_05),CFG8_05_LOAD_INIT_CNT_SPS1);  //load counter IV  in HAL_TSP_PVR_SPSConfig()