Lines Matching refs:_RegCtrl2
41 static REG_Ctrl2* _RegCtrl2 = NULL; variable
182 _RegCtrl2 = (REG_Ctrl2*)(u32BankAddr + 0xE0400UL); //TSP3 0x1702, in HAL_TSP_SetBank()
265 REG16_SET(&_RegCtrl2->CFG_16, CFG_16_PID_BYPASS3_REC); in HAL_TSP_HwPatch()
266 REG16_SET(&_RegCtrl2->CFG_23, CFG_23_PID_BYPASS4_REC); in HAL_TSP_HwPatch()
346 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1); in HAL_TSP_Reset()
351 REG16_SET(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1); in HAL_TSP_Reset()
352 REG16_SET(&_RegCtrl2->CFG_05, CFG_05_RST_CMDQ_FILEIN_TSIF2); in HAL_TSP_Reset()
353 REG16_SET(&_RegCtrl2->CFG_0A, CFG_0A_RST_CMDQ_FILEIN_TSIF3); in HAL_TSP_Reset()
364 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1); in HAL_TSP_Reset()
365 REG16_CLR(&_RegCtrl2->CFG_05, CFG_05_RST_CMDQ_FILEIN_TSIF2); in HAL_TSP_Reset()
366 REG16_CLR(&_RegCtrl2->CFG_0A, CFG_0A_RST_CMDQ_FILEIN_TSIF3); in HAL_TSP_Reset()
378 REG16_SET(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT0); in HAL_TSP_Path_Reset()
379 REG16_SET(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF0 | CFG_12_REG_REST_PDBF0); in HAL_TSP_Path_Reset()
383 REG16_CLR(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF0 | CFG_12_REG_REST_PDBF0); in HAL_TSP_Path_Reset()
384 REG16_CLR(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT0); in HAL_TSP_Path_Reset()
390 REG16_SET(&_RegCtrl2->CFG_00,CFG_00_RST_TS_FIN1); in HAL_TSP_Path_Reset()
391 REG16_SET(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT1); in HAL_TSP_Path_Reset()
392 REG16_SET(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF1 | CFG_12_REG_REST_PDBF1); in HAL_TSP_Path_Reset()
396 REG16_CLR(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF1 | CFG_12_REG_REST_PDBF1); in HAL_TSP_Path_Reset()
397 REG16_CLR(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT1); in HAL_TSP_Path_Reset()
398 REG16_CLR(&_RegCtrl2->CFG_00,CFG_00_RST_TS_FIN1); in HAL_TSP_Path_Reset()
403 REG16_SET(&_RegCtrl2->CFG_05,CFG_05_RST_TS_FIN2); in HAL_TSP_Path_Reset()
404 REG16_SET(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT2); in HAL_TSP_Path_Reset()
405 REG16_SET(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF2 | CFG_12_REG_REST_PDBF2); in HAL_TSP_Path_Reset()
409 REG16_CLR(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF2 | CFG_12_REG_REST_PDBF2); in HAL_TSP_Path_Reset()
410 REG16_CLR(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT2); in HAL_TSP_Path_Reset()
411 REG16_CLR(&_RegCtrl2->CFG_05,CFG_05_RST_TS_FIN2); in HAL_TSP_Path_Reset()
622 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF0); in HAL_TSP_PktBuf_Reset()
625 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF1); in HAL_TSP_PktBuf_Reset()
628 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF2); in HAL_TSP_PktBuf_Reset()
639 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF0); in HAL_TSP_PktBuf_Reset()
642 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF1); in HAL_TSP_PktBuf_Reset()
645 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF2); in HAL_TSP_PktBuf_Reset()
660 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF0); in HAL_TSP_RecvBuf_Reset()
663 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF1); in HAL_TSP_RecvBuf_Reset()
666 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF2); in HAL_TSP_RecvBuf_Reset()
677 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF0); in HAL_TSP_RecvBuf_Reset()
680 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF1); in HAL_TSP_RecvBuf_Reset()
683 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF2); in HAL_TSP_RecvBuf_Reset()
950 …REG16_SET(&_RegCtrl2->CFG_01, CFG_01_TSP_FILE_SEGMENT1); // for wishbone DMA (load firm… in HAL_TSP_TSIF_FileEn()
951 REG16_SET(&_RegCtrl2->CFG_00, CFG_00_TSP_FILE_SEGMENT_TSIF1); in HAL_TSP_TSIF_FileEn()
952 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_TS_DATA_PORT_SEL1); in HAL_TSP_TSIF_FileEn()
953 REG16_SET(&_RegCtrl2->CFG_00, CFG_00_TSP_FILE_IN_TSIF1_EN); //filein enable in HAL_TSP_TSIF_FileEn()
956 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_TSP_FILE_SEGMENT2); in HAL_TSP_TSIF_FileEn()
957 REG16_SET(&_RegCtrl2->CFG_05, CFG_05_TSP_FILE_SEGMENT_TSIF2); in HAL_TSP_TSIF_FileEn()
958 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_TS_DATA_PORT_SEL2); in HAL_TSP_TSIF_FileEn()
959 REG16_SET(&_RegCtrl2->CFG_05, CFG_05_TSP_FILEIN_TSIF2); in HAL_TSP_TSIF_FileEn()
975 REG16_CLR(&_RegCtrl2->CFG_01, CFG_01_TSP_FILE_SEGMENT1); in HAL_TSP_TSIF_FileEn()
976 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_TSP_FILE_SEGMENT_TSIF1); in HAL_TSP_TSIF_FileEn()
977 REG16_CLR(&_RegCtrl2->CFG_01, CFG_01_TS_DATA_PORT_SEL1); in HAL_TSP_TSIF_FileEn()
978 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_TSP_FILE_IN_TSIF1_EN); in HAL_TSP_TSIF_FileEn()
981 REG16_CLR(&_RegCtrl2->CFG_06, CFG_06_TSP_FILE_SEGMENT2); in HAL_TSP_TSIF_FileEn()
982 REG16_CLR(&_RegCtrl2->CFG_05, CFG_05_TSP_FILE_SEGMENT_TSIF2); in HAL_TSP_TSIF_FileEn()
983 REG16_CLR(&_RegCtrl2->CFG_05, CFG_05_TSP_FILEIN_TSIF2); in HAL_TSP_TSIF_FileEn()
984 REG16_CLR(&_RegCtrl2->CFG_06, CFG_06_TS_DATA_PORT_SEL2); in HAL_TSP_TSIF_FileEn()
1266 REG16_MSK_W(&_RegCtrl2->CFG_01, CFG_01_PDFLT2_FILE_SRC, u16Src); in HAL_TSP_ReDirect_File()
1504 …REG16_W(&_RegCtrl2->CFG_02, (REG16_R(&_RegCtrl2->CFG_02) & ~CFG_02_PKT_CHK_SIZE_FIN1) | (CFG_02_PK… in HAL_TSP_Filein_PktSize()
1507 …REG16_W(&_RegCtrl2->CFG_07, (REG16_R(&_RegCtrl2->CFG_07) & ~CFG_07_PKT_CHK_SIZE_FILEIN2) | (CFG_07… in HAL_TSP_Filein_PktSize()
1522 REG32_W(&_RegCtrl2->CFG_30_31, addr); in HAL_TSP_Filein_Addr()
1525 REG32_W(&_RegCtrl2->CFG_35_36, addr); in HAL_TSP_Filein_Addr()
1540 REG32_W(&_RegCtrl2->CFG_32_33, size); in HAL_TSP_Filein_Size()
1543 REG32_W(&_RegCtrl2->CFG_37_38, size); in HAL_TSP_Filein_Size()
1558 REG16_SET(&_RegCtrl2->CFG_34, CFG_34_REG_TSP_FILEIN_CTRL_TSIF1_START); in HAL_TSP_Filein_Start()
1561 REG16_SET(&_RegCtrl2->CFG_39, CFG_39_FILEIN_CTRL_TSIF2_START); in HAL_TSP_Filein_Start()
1612 …REG16_SET(&_RegCtrl2->CFG_34, (CFG_34_REG_TSP_FILEIN_INIT_TRUST_TSIF1 | CFG_34_REG_TSP_FILEIN_CTRL… in HAL_TSP_Filein_Init_Trust_Start()
1615 … REG16_SET(&_RegCtrl2->CFG_39, (CFG_39_FILEIN_INIT_TRUST_TSIF2 | CFG_39_FILEIN_CTRL_TSIF2_START)); in HAL_TSP_Filein_Init_Trust_Start()
1629 REG16_SET(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF0); in HAL_TSP_Filein_Abort()
1632 REG16_SET(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF1); in HAL_TSP_Filein_Abort()
1635 REG16_SET(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF2); in HAL_TSP_Filein_Abort()
1646 REG16_CLR(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF0); in HAL_TSP_Filein_Abort()
1649 REG16_CLR(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF1); in HAL_TSP_Filein_Abort()
1652 REG16_CLR(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF2); in HAL_TSP_Filein_Abort()
1670 REG16_SET(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1); in HAL_TSP_Filein_CmdQRst()
1673 REG16_SET(&_RegCtrl2->CFG_05, CFG_05_RST_CMDQ_FILEIN_TSIF2); in HAL_TSP_Filein_CmdQRst()
1687 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1); in HAL_TSP_Filein_CmdQRst()
1690 REG16_CLR(&_RegCtrl2->CFG_05, CFG_05_RST_CMDQ_FILEIN_TSIF2); in HAL_TSP_Filein_CmdQRst()
1705 …return (CFG_3F_REG_TSIF1_CMD_QUEUE_SIZE - (REG16_R(&_RegCtrl2->CFG_3F) & CFG_3F_REG_TSIF1_CMD_QUEU… in HAL_TSP_Filein_CmdQSlot()
1707 …return (CFG_40_REG_TSIF2_CMD_QUEUE_SIZE - (REG16_R(&_RegCtrl2->CFG_40) & CFG_40_REG_TSIF2_CMD_QUEU… in HAL_TSP_Filein_CmdQSlot()
1720 return (REG16_R(&_RegCtrl2->CFG_3F) & CFG_3F_REG_TSIF1_CMD_QUEUE_WR_CNT); in HAL_TSP_Filein_CmdQCnt()
1722 return (REG16_R(&_RegCtrl2->CFG_40) & CFG_40_REG_TSIF2_CMD_QUEUE_WR_CNT); in HAL_TSP_Filein_CmdQCnt()
1735 …return ((REG16_R(&_RegCtrl2->CFG_3F) & CFG_3F_REG_TSIF1_CMD_QUEUE_WR_LEVEL) >> CFG_3F_REG_TSIF1_CM… in HAL_TSP_Filein_CmdQLv()
1737 …return ((REG16_R(&_RegCtrl2->CFG_40) & CFG_40_REG_TSIF2_CMD_QUEUE_WR_LEVEL) >> CFG_3F_REG_TSIF1_CM… in HAL_TSP_Filein_CmdQLv()
1754 REG16_W(&_RegCtrl2->CFG_03, delay & CFG_03_TSP_FILE_TIMER1); in HAL_TSP_Filein_ByteDelay()
1755 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_TIMER_EN1); in HAL_TSP_Filein_ByteDelay()
1758 REG16_W(&_RegCtrl2->CFG_08, delay & CFG_08_TSP_FILE_TIMER2); in HAL_TSP_Filein_ByteDelay()
1759 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_TSP_TIMER_EN2); in HAL_TSP_Filein_ByteDelay()
1774 REG16_CLR(&_RegCtrl2->CFG_01, CFG_01_TIMER_EN1); in HAL_TSP_Filein_ByteDelay()
1775 REG16_W(&_RegCtrl2->CFG_03, 0x0000); in HAL_TSP_Filein_ByteDelay()
1778 REG16_CLR(&_RegCtrl2->CFG_06, CFG_06_TSP_TIMER_EN2); in HAL_TSP_Filein_ByteDelay()
1779 REG16_W(&_RegCtrl2->CFG_08, 0x0000); in HAL_TSP_Filein_ByteDelay()
1794 return !(REG16_R(&_RegCtrl2->CFG_34) & CFG_34_REG_TSP_FILEIN_CTRL_TSIF1_DONE); in HAL_TSP_Filein_Status()
1796 return !(REG16_R(&_RegCtrl2->CFG_39) & CFG_39_FILEIN_CTRL_TSIF2_DONE); in HAL_TSP_Filein_Status()
1878 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_PKT192_EN1); in HAL_TSP_Filein_PacketMode()
1881 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_TSP_PKT192_EN2); in HAL_TSP_Filein_PacketMode()
1895 REG16_CLR(&_RegCtrl2->CFG_01, CFG_01_PKT192_EN1); in HAL_TSP_Filein_PacketMode()
1898 REG16_CLR(&_RegCtrl2->CFG_06, CFG_06_TSP_PKT192_EN2); in HAL_TSP_Filein_PacketMode()
1917 REG16_CLR(&_RegCtrl2->CFG_01, CFG_01_PKT192_BLK_DISABLE1); in HAL_TSP_Filein_BlockTimeStamp()
1920 REG16_CLR(&_RegCtrl2->CFG_06, CFG_06_TSP_PKT192_BLK_DISABLE2); in HAL_TSP_Filein_BlockTimeStamp()
1934 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_PKT192_BLK_DISABLE1); in HAL_TSP_Filein_BlockTimeStamp()
1937 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_TSP_PKT192_BLK_DISABLE2); in HAL_TSP_Filein_BlockTimeStamp()
1980 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_LPCR2_WLD1); in HAL_TSP_Filein_SetTimeStamp()
1981 REG32_W(&_RegCtrl2->CFG_50_51, u32Stamp); in HAL_TSP_Filein_SetTimeStamp()
1982 REG16_CLR(&_RegCtrl2->CFG_01, CFG_01_LPCR2_WLD1); in HAL_TSP_Filein_SetTimeStamp()
1985 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_LPCR2_WLD2); in HAL_TSP_Filein_SetTimeStamp()
1986 REG32_W(&_RegCtrl2->CFG_52_53, u32Stamp); in HAL_TSP_Filein_SetTimeStamp()
1987 REG16_CLR(&_RegCtrl2->CFG_06, CFG_06_LPCR2_WLD2); in HAL_TSP_Filein_SetTimeStamp()
2046 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_LPCR2_LOAD_TSIF1); in HAL_TSP_Filein_GetTimeStamp()
2047 u32Stamp = REG32_R(&_RegCtrl2->CFG_50_51); in HAL_TSP_Filein_GetTimeStamp()
2048 REG16_SET(&_RegCtrl2->CFG_00, CFG_00_LPCR2_LOAD_TSIF1); in HAL_TSP_Filein_GetTimeStamp()
2051 REG16_CLR(&_RegCtrl2->CFG_05, CFG_05_LPCR2_LOAD_TSIF2); in HAL_TSP_Filein_GetTimeStamp()
2052 u32Stamp = REG32_R(&_RegCtrl2->CFG_52_53); in HAL_TSP_Filein_GetTimeStamp()
2053 REG16_SET(&_RegCtrl2->CFG_05, CFG_05_LPCR2_LOAD_TSIF2); in HAL_TSP_Filein_GetTimeStamp()
2069 return REG32_R(&_RegCtrl2->CFG_42_43); in HAL_TSP_Filein_PktTimeStamp()
2071 return REG32_R(&_RegCtrl2->CFG_44_45); in HAL_TSP_Filein_PktTimeStamp()
2086 *pu32Addr = (MS_PHY)(REG32_R(&_RegCtrl2->CFG_6A_6B) & CFG_6A_6B_TSP2MI_RADDR_S_TSIF1); in HAL_TSP_Filein_GetCurAddr()
2089 *pu32Addr = (MS_PHY)(REG32_R(&_RegCtrl2->CFG_6C_6D) & CFG_6C_6D_TSP2MI_RADDR_S_TSIF2); in HAL_TSP_Filein_GetCurAddr()
2148 REG16_W(&_RegCtrl2->CFG_75, (u32Key & CFG_75_FI_MOBF_INDEC_TSIF1_MASK)); in HAL_TSP_Filein_MOBF_Enable()
2151 REG16_W(&_RegCtrl2->CFG_76, (u32Key & CFG_76_FI_MOBF_INDEC_TSIF2_MASK)); in HAL_TSP_Filein_MOBF_Enable()
2165 REG16_W(&_RegCtrl2->CFG_75, 0); in HAL_TSP_Filein_MOBF_Enable()
2168 REG16_W(&_RegCtrl2->CFG_76, 0); in HAL_TSP_Filein_MOBF_Enable()
2586 REG16_MSK_W(&_RegCtrl2->CFG_01, CFG_01_PCR0_SRC_MASK, src << CFG_01_PCR0_SRC_SHIFT); in HAL_TSP_PcrFlt_SetSrc()
2590 REG16_MSK_W(&_RegCtrl2->CFG_01, CFG_01_PCR1_SRC_MASK, src << CFG_01_PCR1_SRC_SHIFT); in HAL_TSP_PcrFlt_SetSrc()
2606 … *pPcrSrc = (REG16_R(&_RegCtrl2->CFG_01) & CFG_01_PCR0_SRC_MASK) >> CFG_01_PCR0_SRC_SHIFT; in HAL_TSP_PcrFlt_GetSrc()
2610 … *pPcrSrc = (REG16_R(&_RegCtrl2->CFG_01) & CFG_01_PCR1_SRC_MASK) >> CFG_01_PCR1_SRC_SHIFT; in HAL_TSP_PcrFlt_GetSrc()
3091 return REG16_R(&_RegCtrl2->CFG_70) & CFG_70_MATCHECED_VPID_3D_MASK; in HAL_TSP_FIFO_PidHit()
3095 return REG16_R(&_RegCtrl2->CFG_71) & CFG_71_MATCHECED_APID_B_MASK; in HAL_TSP_FIFO_PidHit()
4195 REG16_SET((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD0); in HAL_PVR_SetPVRTimeStamp_Stream()
4197 REG32_W(&_RegCtrl2->CFG_56_57, u32Stamp); in HAL_PVR_SetPVRTimeStamp_Stream()
4199 REG16_CLR((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD0); in HAL_PVR_SetPVRTimeStamp_Stream()
4202 REG16_SET((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD1); in HAL_PVR_SetPVRTimeStamp_Stream()
4204 REG32_W(&_RegCtrl2->CFG_58_59, u32Stamp); in HAL_PVR_SetPVRTimeStamp_Stream()
4206 REG16_CLR((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD1); in HAL_PVR_SetPVRTimeStamp_Stream()
4352 REG16_SET((&_RegCtrl2->CFG_12), CFG_12_TIMESTAMP_SEL_PVR1 << (u32PVREng)); in HAL_PVR_TimeStamp_Sel()
4356 REG16_CLR((&_RegCtrl2->CFG_12), CFG_12_TIMESTAMP_SEL_PVR1 << (u32PVREng)); in HAL_PVR_TimeStamp_Sel()
4411 REG16_SET((&_RegCtrl2->CFG_13), CFG_13_LPCR_EN0 << (u32pktDmxId*2)); in HAL_PVR_TimeStamp_Stream_En()
4415 REG16_CLR((&_RegCtrl2->CFG_13), CFG_13_LPCR_EN0 << (u32pktDmxId*2)); in HAL_PVR_TimeStamp_Stream_En()
4700 REG16_MSK_W(&_RegCtrl2->CFG_11, CFG_11_RECEIVE_BUF0_SRC, inputSrc<<(bufIdx * 2)); in HAL_TSP_Set_RcvBuf_Src()
4703 REG16_MSK_W(&_RegCtrl2->CFG_11, CFG_11_RECEIVE_BUF1_SRC, inputSrc<<(bufIdx * 2)); in HAL_TSP_Set_RcvBuf_Src()
4706 REG16_MSK_W(&_RegCtrl2->CFG_11, CFG_11_RECEIVE_BUF2_SRC, inputSrc<<(bufIdx * 2)); in HAL_TSP_Set_RcvBuf_Src()