Lines Matching refs:_RegCtrl
40 static REG_Ctrl* _RegCtrl = NULL; variable
159 REG32_W(&_RegCtrl->Idr_Addr, (MS_VIRT)preg); in TSP32_IdrW()
160 REG32_W(&_RegCtrl->Idr_Write, value); in TSP32_IdrW()
161 REG16_W(&_RegCtrl->Idr_Ctrl, TSP_IDR_START | TSP_IDR_WRITE); in TSP32_IdrW()
172 REG32_W(&_RegCtrl->Idr_Addr, (MS_VIRT)preg); in TSP32_IdrR()
173 REG16_W(&_RegCtrl->Idr_Ctrl, TSP_IDR_START | TSP_IDR_READ); in TSP32_IdrR()
175 return REG32_R(&_RegCtrl->Idr_Read); in TSP32_IdrR()
181 _RegCtrl = (REG_Ctrl*)(u32BankAddr + 0x2A00UL); //TSP0 0x1015, TSP1 0x1016 in HAL_TSP_SetBank()
250 REG16_SET(&_RegCtrl->PktChkSizeFilein, TSP_HW_STANDBY_MODE); in HAL_TSP_HwPatch()
255 …REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_BYTE_ADDR_DMA|TSP_HW_CFG4_ALT_TS_SIZE|TSP_HW_CFG4_WST… in HAL_TSP_HwPatch()
261 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_STANDBY); in HAL_TSP_HwPatch()
264 REG16_SET(&_RegCtrl->reg15b4, TSP_PVR_PID_BYPASS|TSP_PVR_PID_BYPASS2); in HAL_TSP_HwPatch()
268 REG16_SET(&_RegCtrl->reg15b8, TSP_REMOVE_DUP_AV_PKT); in HAL_TSP_HwPatch()
270 …REG16_SET(&_RegCtrl->HW2_Config3, TSP_VQ2PINGPONG_EN | TSP_RM_PKT_DEMUX_PIPE /*| TSP_PVR1_ALIGN_EN… in HAL_TSP_HwPatch()
273 …REG16_SET(&_RegCtrl->reg160C, TSP_DOUBLE_BUF_DESC/*| TSP_VQTX0_BLOCK_DIS|TSP_VQTX2_BLOCK_DIS|TSP_V… in HAL_TSP_HwPatch()
274 REG16_SET(&_RegCtrl->reg160E, TSP_RM_DMA_GLITCH); in HAL_TSP_HwPatch()
278 REG16_SET(&_RegCtrl->TSP_Cfg5, TSP_SYSTIME_MODE); in HAL_TSP_HwPatch()
279 REG16_SET(&_RegCtrl->PVRConfig, TSP_MATCH_PID_LD); in HAL_TSP_HwPatch()
290 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_DATA_CHK_2T); in HAL_TSP_HwPatch()
310 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_SYNC_RISING_DETECT | TSP_VALID_FALLING_DETECT); in HAL_TSP_HwPatch()
345 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_PVR_CMD_QUEUE_ENABLE); in HAL_TSP_Reset()
350 REG16_SET(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_CMDQ_RESET); in HAL_TSP_Reset()
354 REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_WB_DMA_RESET); in HAL_TSP_Reset()
355 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_SW_RST); in HAL_TSP_Reset()
359 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_SW_RST); in HAL_TSP_Reset()
361 REG16_CLR(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_WB_DMA_RESET); in HAL_TSP_Reset()
363 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_CMDQ_RESET); in HAL_TSP_Reset()
377 REG16_SET(&_RegCtrl->reg160C,TSP_TIMESTAMP_RESET); in HAL_TSP_Path_Reset()
385 REG16_CLR(&_RegCtrl->reg160C,TSP_TIMESTAMP_RESET); in HAL_TSP_Path_Reset()
514 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_CPU_EN); in HAL_TSP_CPU()
518 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_CPU_EN); in HAL_TSP_CPU()
526 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_CPU_EN); in HAL_TSP_ResetCPU()
530 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_CPU_EN); in HAL_TSP_ResetCPU()
546 REG32_W(&_RegCtrl->Cpu_Base, 0); // 16 bytes address unit in HAL_TSP_LoadFW()
554 … REG16_W(&_RegCtrl->Dnld_Ctrl_Addr, (MS_U16)(u32DnldCtrl & TSP_DNLD_ADDR_MASK)); // oneway register in HAL_TSP_LoadFW()
555 REG16_MSK_W(&_RegCtrl->Dnld_AddrH, TSP_DMA_RADDR_MSB_MASK, (MS_U16)u32DnldCtrl1); in HAL_TSP_LoadFW()
556 REG16_W(&_RegCtrl->Dnld_Ctrl_Size, _TSP_QMEM_SIZE); in HAL_TSP_LoadFW()
557 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_DNLD_START| TSP_CTRL_DNLD_DONE); in HAL_TSP_LoadFW()
558 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_DNLD_START); in HAL_TSP_LoadFW()
562 while (!(REG16_R(&_RegCtrl->TSP_Ctrl) & TSP_CTRL_DNLD_DONE)) in HAL_TSP_LoadFW()
568 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_DNLD_START| TSP_CTRL_DNLD_DONE); in HAL_TSP_LoadFW()
570 REG32_W(&_RegCtrl->Qmem_Imask, _TSP_QMEM_I_MASK); in HAL_TSP_LoadFW()
571 REG32_W(&_RegCtrl->Qmem_Ibase, _TSP_QMEM_I_ADDR_HIT); in HAL_TSP_LoadFW()
572 REG32_W(&_RegCtrl->Qmem_Dmask, _TSP_QMEM_D_MASK); in HAL_TSP_LoadFW()
573 REG32_W(&_RegCtrl->Qmem_Dbase, _TSP_QMEM_D_ADDR_HIT); in HAL_TSP_LoadFW()
722 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TSIF0_ENABLE); in HAL_TSP_TSIF_LiveEn()
725 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TSIF1_ENABLE); in HAL_TSP_TSIF_LiveEn()
728 REG32_SET(&_RegCtrl->PVR2_Config, TSP_TS_IF2_EN); in HAL_TSP_TSIF_LiveEn()
739 REG16_CLR(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TSIF0_ENABLE); in HAL_TSP_TSIF_LiveEn()
742 REG16_CLR(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TSIF1_ENABLE); in HAL_TSP_TSIF_LiveEn()
745 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_TS_IF2_EN); in HAL_TSP_TSIF_LiveEn()
945 …REG16_SET(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_PVR_CMD_QUEUE_ENABLE); // for wishbone DMA (load firm… in HAL_TSP_TSIF_FileEn()
946 … REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_DATA_PORT_SEL); //Tsif0 output is live TS in HAL_TSP_TSIF_FileEn()
947 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_TSFILE_EN); //filein enable in HAL_TSP_TSIF_FileEn()
970 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_PVR_CMD_QUEUE_ENABLE); in HAL_TSP_TSIF_FileEn()
971 REG16_CLR(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_DATA_PORT_SEL); in HAL_TSP_TSIF_FileEn()
972 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_TSFILE_EN); in HAL_TSP_TSIF_FileEn()
1001 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TS_DATA0_SWAP); in HAL_TSP_TSIF_BitSwap()
1004 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TS_DATA1_SWAP); in HAL_TSP_TSIF_BitSwap()
1007 REG32_SET(&_RegCtrl->PVR2_Config, TSP_TS_DATA2_SWAP); in HAL_TSP_TSIF_BitSwap()
1018 REG16_CLR(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TS_DATA0_SWAP); in HAL_TSP_TSIF_BitSwap()
1021 REG16_CLR(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TS_DATA1_SWAP); in HAL_TSP_TSIF_BitSwap()
1024 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_TS_DATA2_SWAP); in HAL_TSP_TSIF_BitSwap()
1041 REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_EXTSYNC); in HAL_TSP_TSIF_ExtSync()
1044 REG16_SET(&_RegCtrl->Hw_Config2, TSP_HW_CFG2_TSIF1_EXTSYNC); in HAL_TSP_TSIF_ExtSync()
1047 REG32_SET(&_RegCtrl->PVR2_Config, TSP_EXT_SYNC_SEL2); in HAL_TSP_TSIF_ExtSync()
1060 REG16_CLR(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_EXTSYNC); in HAL_TSP_TSIF_ExtSync()
1063 REG16_CLR(&_RegCtrl->Hw_Config2, TSP_HW_CFG2_TSIF1_EXTSYNC); in HAL_TSP_TSIF_ExtSync()
1066 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_EXT_SYNC_SEL2); in HAL_TSP_TSIF_ExtSync()
1082 REG16_SET(&(_RegCtrl->TSP_Ctrl2), TSP_AV_DIRECT_STOP); in HAL_TSP_Filein_Bypass()
1085 REG16_SET(&(_RegCtrl->TSP_Ctrl2), TSP_AV_DIRECT_STOP1); in HAL_TSP_Filein_Bypass()
1088 REG16_SET(&(_RegCtrl->TSP_Ctrl2), TSP_AV_DIRECT_STOP2); in HAL_TSP_Filein_Bypass()
1101 REG16_CLR(&(_RegCtrl->TSP_Ctrl2), TSP_AV_DIRECT_STOP); in HAL_TSP_Filein_Bypass()
1104 REG16_CLR(&(_RegCtrl->TSP_Ctrl2), TSP_AV_DIRECT_STOP1); in HAL_TSP_Filein_Bypass()
1107 REG16_CLR(&(_RegCtrl->TSP_Ctrl2), TSP_AV_DIRECT_STOP2); in HAL_TSP_Filein_Bypass()
1123 REG16_SET(&(_RegCtrl->Hw_Config0), TSP_HW_CFG0_TSIF0_PARL); in HAL_TSP_TSIF_Parl()
1126 REG16_SET(&(_RegCtrl->Hw_Config2), TSP_HW_CFG2_TSIF1_PARL); in HAL_TSP_TSIF_Parl()
1129 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_P_SEL2); in HAL_TSP_TSIF_Parl()
1140 REG16_CLR(&(_RegCtrl->Hw_Config0), TSP_HW_CFG0_TSIF0_PARL); in HAL_TSP_TSIF_Parl()
1143 REG16_CLR(&(_RegCtrl->Hw_Config2), TSP_HW_CFG2_TSIF1_PARL); in HAL_TSP_TSIF_Parl()
1146 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_P_SEL2); in HAL_TSP_TSIF_Parl()
1412 REG16_SET(&_RegCtrl->reg15b4, TSP_BD_AUD_EN); in HAL_TSP_BD_AUD_En()
1415 REG16_SET(&_RegCtrl->reg15b4, TSP_BD2_AUD_EN); in HAL_TSP_BD_AUD_En()
1427 REG16_CLR(&_RegCtrl->reg15b4, TSP_BD_AUD_EN); in HAL_TSP_BD_AUD_En()
1430 REG16_CLR(&_RegCtrl->reg15b4, TSP_BD2_AUD_EN); in HAL_TSP_BD_AUD_En()
1500 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_ALT_TS_SIZE); in HAL_TSP_Filein_PktSize()
1501 …REG16_W(&_RegCtrl->PktChkSizeFilein, (REG16_R(&_RegCtrl->PktChkSizeFilein) & ~TSP_PKT_SIZE_MASK) |… in HAL_TSP_Filein_PktSize()
1519 REG32_W(&_RegCtrl->TsDma_Addr, addr); in HAL_TSP_Filein_Addr()
1537 REG32_W(&_RegCtrl->TsDma_Size, size); in HAL_TSP_Filein_Size()
1555 REG16_SET(&_RegCtrl->TsDma_Ctrl, TSP_TSDMA_CTRL_START); in HAL_TSP_Filein_Start()
1573 REG16_SET(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_FILEIN_PAUSE); in HAL_TSP_File_Pause()
1591 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_FILEIN_PAUSE); in HAL_TSP_File_Resume()
1609 REG16_SET(&_RegCtrl->TsDma_Ctrl, (TSP_TSDMA_INIT_TRUST | TSP_TSDMA_CTRL_START)); in HAL_TSP_Filein_Init_Trust_Start()
1667 REG16_SET(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_CMDQ_RESET); in HAL_TSP_Filein_CmdQRst()
1684 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_CMDQ_RESET); in HAL_TSP_Filein_CmdQRst()
1703 …return (TSP_CMDQ_SIZE - ((REG16_R(&_RegCtrl->TsDma_mdQ) & TSP_CMDQ_CNT_MASK) >> TSP_CMDQ_CNT_SHFT)… in HAL_TSP_Filein_CmdQSlot()
1718 return ((REG16_R(&_RegCtrl->TsDma_mdQ) & TSP_CMDQ_CNT_MASK) >> TSP_CMDQ_CNT_SHFT); in HAL_TSP_Filein_CmdQCnt()
1733 … return ((REG16_R(&_RegCtrl->TsDma_Ctrl) & TSP_CMDQ_WR_LEVEL_MASK) >> TSP_CMDQ_WR_LEVEL_SHFT); in HAL_TSP_Filein_CmdQLv()
1750 REG32_W(&_RegCtrl->TsFileIn_Timer, delay & TSP_FILE_TIMER_MASK); in HAL_TSP_Filein_ByteDelay()
1751 REG16_SET(&_RegCtrl->reg15b4, TSP_FILEIN_BYTETIMER_ENABLE); in HAL_TSP_Filein_ByteDelay()
1770 REG16_CLR(&_RegCtrl->reg15b4, TSP_FILEIN_BYTETIMER_ENABLE); in HAL_TSP_Filein_ByteDelay()
1771 REG32_W(&_RegCtrl->TsFileIn_Timer, 0x0000); in HAL_TSP_Filein_ByteDelay()
1792 return !(REG16_R(&_RegCtrl->TsDma_Ctrl) & TSP_TSDMA_FILEIN_DONE); in HAL_TSP_Filein_Status()
1820 if (REG16_R(&_RegCtrl->TSP_Ctrl1) & TSP_CTRL1_FILEIN_PAUSE ) in HAL_TSP_Filein_GetState()
1875 REG16_SET(&_RegCtrl->reg160C, TSP_FILEIN192_EN); in HAL_TSP_Filein_PacketMode()
1892 REG16_CLR(&_RegCtrl->reg160C, TSP_FILEIN192_EN); in HAL_TSP_Filein_PacketMode()
1914 REG16_CLR(&_RegCtrl->PktChkSizeFilein, TSP_PKT192_BLK_DIS_FIN); in HAL_TSP_Filein_BlockTimeStamp()
1931 REG16_SET(&_RegCtrl->PktChkSizeFilein, TSP_PKT192_BLK_DIS_FIN); in HAL_TSP_Filein_BlockTimeStamp()
1975 REG16_SET(&_RegCtrl->reg160C, TSP_LPCR2_WLD); in HAL_TSP_Filein_SetTimeStamp()
1976 REG32_W(&_RegCtrl->LPcr2, u32Stamp); in HAL_TSP_Filein_SetTimeStamp()
1977 REG16_CLR(&_RegCtrl->reg160C, TSP_LPCR2_WLD); in HAL_TSP_Filein_SetTimeStamp()
2041 REG16_CLR(&_RegCtrl->reg160C, TSP_LPCR2_RLD); in HAL_TSP_Filein_GetTimeStamp()
2042 u32Stamp = REG32_R(&_RegCtrl->LPcr2); in HAL_TSP_Filein_GetTimeStamp()
2043 REG16_SET(&_RegCtrl->reg160C, TSP_LPCR2_RLD); in HAL_TSP_Filein_GetTimeStamp()
2067 return REG32_R(&_RegCtrl->TimeStamp_FileIn); in HAL_TSP_Filein_PktTimeStamp()
2083 *pu32Addr = (MS_PHY)(REG32_R(&_RegCtrl->TsFileIn_RPtr) & TSP_FILE_RPTR_MASK); in HAL_TSP_Filein_GetCurAddr()
2145 REG16_W(&_RegCtrl->Mobf_Filein_Idx, (u32Key & TSP_MOBF_FILEIN_MASK)); in HAL_TSP_Filein_MOBF_Enable()
2162 REG16_W(&_RegCtrl->Mobf_Filein_Idx, 0); in HAL_TSP_Filein_MOBF_Enable()
2258 REG16_SET(&_RegCtrl->TSP_Cfg5, TSP_SEC_DMA_BURST_EN); in HAL_TSP_SecFlt_BurstLen()
2259 REG16_MSK_W(&_RegCtrl->Hw_Config4, TSP_HW_DMA_MODE_MASK, (burstMode << TSP_HW_DMA_MODE_SHIFT)); in HAL_TSP_SecFlt_BurstLen()
2528 REG16_SET(&_RegCtrl->PIDFLT_PCR0, TSP_PIDFLT_PCR0_EN); in HAL_TSP_PcrFlt_Enable()
2532 REG16_CLR(&_RegCtrl->PIDFLT_PCR0, TSP_PIDFLT_PCR0_EN); in HAL_TSP_PcrFlt_Enable()
2538 REG16_SET(&_RegCtrl->PIDFLT_PCR1, TSP_PIDFLT_PCR1_EN); in HAL_TSP_PcrFlt_Enable()
2542 REG16_CLR(&_RegCtrl->PIDFLT_PCR1, TSP_PIDFLT_PCR1_EN); in HAL_TSP_PcrFlt_Enable()
2555 REG16_MSK_W(&_RegCtrl->PIDFLT_PCR0, TSP_PIDFLT_PCR0_PID_MASK, u32Pid); in HAL_TSP_PcrFlt_SetPid()
2558 REG16_MSK_W(&_RegCtrl->PIDFLT_PCR1, TSP_PIDFLT_PCR1_PID_MASK, u32Pid); in HAL_TSP_PcrFlt_SetPid()
2571 return (REG16_R(&_RegCtrl->PIDFLT_PCR0) & TSP_PIDFLT_PCR0_PID_MASK); in HAL_TSP_PcrFlt_GetPid()
2573 return (REG16_R(&_RegCtrl->PIDFLT_PCR1) & TSP_PIDFLT_PCR1_PID_MASK); in HAL_TSP_PcrFlt_GetPid()
2654 REG16_SET(&_RegCtrl->PCR_Cfg, TSP_PCR0_READ); in HAL_TSP_PcrFlt_GetPcr()
2655 *pu32Pcr = REG32_R(&_RegCtrl->HWPCR0_L); in HAL_TSP_PcrFlt_GetPcr()
2656 *pu32Pcr_H = REG32_R(&_RegCtrl->HWPCR0_H) & 0x1; in HAL_TSP_PcrFlt_GetPcr()
2657 REG16_CLR(&_RegCtrl->PCR_Cfg, TSP_PCR0_READ); in HAL_TSP_PcrFlt_GetPcr()
2660 REG16_SET(&_RegCtrl->PCR_Cfg, TSP_PCR1_READ); in HAL_TSP_PcrFlt_GetPcr()
2661 *pu32Pcr = REG32_R(&_RegCtrl->HWPCR1_L); in HAL_TSP_PcrFlt_GetPcr()
2662 *pu32Pcr_H = REG32_R(&_RegCtrl->HWPCR1_H) & 0x1; in HAL_TSP_PcrFlt_GetPcr()
2663 REG16_CLR(&_RegCtrl->PCR_Cfg, TSP_PCR1_READ); in HAL_TSP_PcrFlt_GetPcr()
2675 REG16_CLR(&_RegCtrl->PCR_Cfg, TSP_PCR0_RESET); in HAL_TSP_PcrFlt_Reset()
2676 REG16_SET(&_RegCtrl->PCR_Cfg, TSP_PCR0_RESET); in HAL_TSP_PcrFlt_Reset()
2679 REG16_CLR(&_RegCtrl->PCR_Cfg, TSP_PCR1_RESET); in HAL_TSP_PcrFlt_Reset()
2680 REG16_SET(&_RegCtrl->PCR_Cfg, TSP_PCR1_RESET); in HAL_TSP_PcrFlt_Reset()
2694 REG16_W(&_RegCtrl->SwInt_Stat1_L, in HAL_TSP_PcrFlt_ClearInt()
2695 (REG16_R(&_RegCtrl->SwInt_Stat1_L) & (~TSP_HWINT2_STATUS_MASK)) | in HAL_TSP_PcrFlt_ClearInt()
2700 REG16_W(&_RegCtrl->SwInt_Stat1_L, in HAL_TSP_PcrFlt_ClearInt()
2701 (REG16_R(&_RegCtrl->SwInt_Stat1_L) & (~TSP_HWINT2_STATUS_MASK)) | in HAL_TSP_PcrFlt_ClearInt()
2818 REG16_SET(&_RegCtrl->TSP_Cfg5, TSP_SYSTIME_MODE); in HAL_TSP_STC64_Mode_En()
2822 REG16_CLR(&_RegCtrl->TSP_Cfg5, TSP_SYSTIME_MODE); in HAL_TSP_STC64_Mode_En()
2831 REG32_W(&_RegCtrl->Pcr_L, stcL); in HAL_TSP_STC64_Set()
2832 REG32_W(&_RegCtrl->Pcr_H, stcH); in HAL_TSP_STC64_Set()
2835 REG32_W(&_RegCtrl->PCR64_2_L, stcL); in HAL_TSP_STC64_Set()
2836 REG32_W(&_RegCtrl->PCR64_2_H, stcH); in HAL_TSP_STC64_Set()
2846 REG16_CLR(&_RegCtrl->reg15b8, TSP_cnt_33b_ld); in HAL_TSP_STC64_Get()
2847 *pStcH = REG32_R(&_RegCtrl->Pcr_H); in HAL_TSP_STC64_Get()
2848 *pStcL = REG32_R(&_RegCtrl->Pcr_L); in HAL_TSP_STC64_Get()
2849 REG16_SET(&_RegCtrl->reg15b8, TSP_cnt_33b_ld); in HAL_TSP_STC64_Get()
2852 REG16_CLR(&_RegCtrl->reg15b8, TSP_64bit_PCR2_ld); in HAL_TSP_STC64_Get()
2853 *pStcH = REG32_R(&_RegCtrl->PCR64_2_H); in HAL_TSP_STC64_Get()
2854 *pStcL = REG32_R(&_RegCtrl->PCR64_2_L); in HAL_TSP_STC64_Get()
2855 REG16_SET(&_RegCtrl->reg15b8, TSP_64bit_PCR2_ld); in HAL_TSP_STC64_Get()
2864 REG16_W(&_RegCtrl->Pcr_H_CmdQ, stcH & TSP_REG_PCR_CMDQ_H); in HAL_TSP_STC33_CmdQSet()
2865 REG32_W(&_RegCtrl->Pcr_L_CmdQ, stcL); in HAL_TSP_STC33_CmdQSet()
2870 REG16_CLR(&_RegCtrl->reg15b8, TSP_cnt_33b_ld); in HAL_TSP_STC33_CmdQGet()
2871 *pStcH = REG16_R(&_RegCtrl->Pcr_H_CmdQ) & TSP_REG_PCR_CMDQ_H; in HAL_TSP_STC33_CmdQGet()
2872 *pStcL = REG32_R(&_RegCtrl->Pcr_L_CmdQ); in HAL_TSP_STC33_CmdQGet()
2873 REG16_SET(&_RegCtrl->reg15b8, TSP_cnt_33b_ld); in HAL_TSP_STC33_CmdQGet()
2881 … REG16_MSK_W(&_RegCtrl->FIFO_Src, TSP_VID_SRC_MASK, ((MS_U16)pktDmxId) << TSP_VID_SRC_SHIFT); in HAL_TSP_FIFO_SetSrc()
2884 … REG16_MSK_W(&_RegCtrl->FIFO_Src, TSP_VID3D_SRC_MASK, ((MS_U16)pktDmxId) << TSP_VID3D_SRC_SHIFT); in HAL_TSP_FIFO_SetSrc()
2887 … REG16_MSK_W(&_RegCtrl->FIFO_Src, TSP_AUD_SRC_MASK, ((MS_U16)pktDmxId) << TSP_AUD_SRC_SHIFT); in HAL_TSP_FIFO_SetSrc()
2890 … REG16_MSK_W(&_RegCtrl->FIFO_Src, TSP_AUDB_SRC_MASK, ((MS_U16)pktDmxId) << TSP_AUDB_SRC_SHIFT); in HAL_TSP_FIFO_SetSrc()
2902 *pktDmxId = ((REG16_R(&_RegCtrl->FIFO_Src)) & TSP_VID_SRC_MASK) >> TSP_VID_SRC_SHIFT; in HAL_TSP_FIFO_GetSrc()
2905 … *pktDmxId = ((REG16_R(&_RegCtrl->FIFO_Src)) & TSP_VID3D_SRC_MASK) >> TSP_VID3D_SRC_SHIFT; in HAL_TSP_FIFO_GetSrc()
2908 *pktDmxId = ((REG16_R(&_RegCtrl->FIFO_Src)) & TSP_AUD_SRC_MASK) >> TSP_AUD_SRC_SHIFT; in HAL_TSP_FIFO_GetSrc()
2911 *pktDmxId = ((REG16_R(&_RegCtrl->FIFO_Src)) & TSP_AUDB_SRC_MASK) >> TSP_AUDB_SRC_SHIFT; in HAL_TSP_FIFO_GetSrc()
2921 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_VID_EN); in HAL_TSP_FIFO_ClearAll()
2922 REG16_CLR(&_RegCtrl->TSP_Ctrl2, TSP_PS_VID_3D_EN); in HAL_TSP_FIFO_ClearAll()
2923 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUD_EN); in HAL_TSP_FIFO_ClearAll()
2924 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDB_EN); in HAL_TSP_FIFO_ClearAll()
2925 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDC_EN); in HAL_TSP_FIFO_ClearAll()
2926 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDD_EN); in HAL_TSP_FIFO_ClearAll()
2935 REG16_SET(&_RegCtrl->reg15b4,TSP_AVFIFO_RD_EN); in HAL_TSP_FIFO_Connect()
2939 REG16_CLR(&_RegCtrl->reg15b4,TSP_AVFIFO_RD_EN); in HAL_TSP_FIFO_Connect()
2947 return (REG16_R(&_RegCtrl->PKT_CNT) & TSP_PKT_CNT_MASK); in HAL_TSP_FIFO_ReadPkt()
2986 REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_VPID_BYPASS); in HAL_TSP_Flt_Bypass()
2989 REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_APID_BYPASS); in HAL_TSP_Flt_Bypass()
3006 REG16_CLR(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_VPID_BYPASS); in HAL_TSP_Flt_Bypass()
3009 REG16_CLR(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_APID_BYPASS); in HAL_TSP_Flt_Bypass()
3041 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_VID_EN); in HAL_TSP_FIFO_Bypass()
3044 REG16_SET(&_RegCtrl->TSP_Ctrl2, TSP_PS_VID_3D_EN); in HAL_TSP_FIFO_Bypass()
3047 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUD_EN); in HAL_TSP_FIFO_Bypass()
3050 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDB_EN); in HAL_TSP_FIFO_Bypass()
3061 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_VID_EN); in HAL_TSP_FIFO_Bypass()
3064 REG16_CLR(&_RegCtrl->TSP_Ctrl2, TSP_PS_VID_3D_EN); in HAL_TSP_FIFO_Bypass()
3067 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUD_EN); in HAL_TSP_FIFO_Bypass()
3070 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDB_EN); in HAL_TSP_FIFO_Bypass()
3089 return REG16_R(&_RegCtrl->Vd_Pid_Hit) & TSP_VPID_MASK; in HAL_TSP_FIFO_PidHit()
3093 return REG16_R(&_RegCtrl->Aud_Pid_Hit) & TSP_APID_MASK; in HAL_TSP_FIFO_PidHit()
3108 REG16_SET(&_RegCtrl->reg160E, TSP_RESET_VFIFO); in HAL_TSP_FIFO_Reset()
3111 REG16_SET(&_RegCtrl->reg160E, TSP_RESET_VFIFO3D); in HAL_TSP_FIFO_Reset()
3115 REG16_SET(&_RegCtrl->reg160E, TSP_RESET_AFIFO); in HAL_TSP_FIFO_Reset()
3118 REG16_SET(&_RegCtrl->reg160E, TSP_RESET_AFIFO2); in HAL_TSP_FIFO_Reset()
3129 REG16_CLR(&_RegCtrl->reg160E, TSP_RESET_VFIFO); in HAL_TSP_FIFO_Reset()
3132 REG16_CLR(&_RegCtrl->reg160E, TSP_RESET_VFIFO3D); in HAL_TSP_FIFO_Reset()
3136 REG16_CLR(&_RegCtrl->reg160E, TSP_RESET_AFIFO); in HAL_TSP_FIFO_Reset()
3139 REG16_CLR(&_RegCtrl->reg160E, TSP_RESET_AFIFO2); in HAL_TSP_FIFO_Reset()
3202 REG32_SET(&_RegCtrl->PVR2_Config, TSP_V_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
3205 REG32_SET(&_RegCtrl->PVR2_Config, TSP_V3d_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
3208 REG32_SET(&_RegCtrl->PVR2_Config, TSP_A_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
3211 REG32_SET(&_RegCtrl->PVR2_Config, TSP_AD_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
3222 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_V_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
3225 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_V3d_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
3228 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_A_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
3231 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_AD_BLOCK_DIS); in HAL_TSP_FIFO_BlockDis()
3245 u32Matched = REG16_R(&_RegCtrl->reg160E) & TSP_RESET_VFIFO; in HAL_TSP_FIFO_IsReset()
3248 u32Matched = REG16_R(&_RegCtrl->reg160E) & TSP_RESET_VFIFO3D; in HAL_TSP_FIFO_IsReset()
3251 u32Matched = REG16_R(&_RegCtrl->reg160E) & TSP_RESET_AFIFO; in HAL_TSP_FIFO_IsReset()
3254 u32Matched = REG16_R(&_RegCtrl->reg160E) & TSP_RESET_AFIFO2; in HAL_TSP_FIFO_IsReset()
3300 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_VFIFO_LEVEL) >> TSP_VFIFO_LEVEL_SHFT; in HAL_TSP_FIFO_Level()
3302 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_VFIFO3D_LEVEL) >> TSP_VFIFO3D_LEVEL_SHFT; in HAL_TSP_FIFO_Level()
3304 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_AFIFO_LEVEL) >> TSP_AFIFO_LEVEL_SHFT; in HAL_TSP_FIFO_Level()
3306 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_AFIFOB_LEVEL) >> TSP_AFIFOB_LEVEL_SHFT; in HAL_TSP_FIFO_Level()
3317 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_VFIFO_FULL) >> TSP_VFIFO_FULL_SHFT; in HAL_TSP_FIFO_Overflow()
3319 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_VFIFO3D_FULL) >> TSP_VFIFO3D_FULL_SHFT; in HAL_TSP_FIFO_Overflow()
3321 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_AFIFO_FULL) >> TSP_AFIFO_FULL_SHFT; in HAL_TSP_FIFO_Overflow()
3323 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_AFIFOB_FULL) >> TSP_AFIFOB_FULL_SHFT; in HAL_TSP_FIFO_Overflow()
3334 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_VFIFO_EMPTY) >> TSP_VFIFO_EMPTY_SHFT; in HAL_TSP_FIFO_Empty()
3336 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_VFIFO3D_EMPTY) >> TSP_VFIFO3D_EMPTY_SHFT; in HAL_TSP_FIFO_Empty()
3338 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_AFIFO_EMPTY) >> TSP_AFIFO_EMPTY_SHFT; in HAL_TSP_FIFO_Empty()
3340 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_AFIFOB_EMPTY) >> TSP_AFIFOB_EMPTY_SHFT; in HAL_TSP_FIFO_Empty()
3354 …REG16_W(&_RegCtrl->VQ0_CTRL, (REG16_R(&_RegCtrl->VQ0_CTRL) & (~TSP_VQ0_WR_THRESHOLD_MASK)) | ((0x8… in _HAL_TSP_VQ_TxConfig()
3355 …REG16_W(&_RegCtrl->VQ0_CTRL, (REG16_R(&_RegCtrl->VQ0_CTRL) & (~TSP_VQ0_FORCE_FIRE_CNT_1K_MASK)) | … in _HAL_TSP_VQ_TxConfig()
3358 …REG16_W(&_RegCtrl->VQ1_Config, (REG16_R(&_RegCtrl->VQ1_Config) & (~TSP_VQ1_WR_THRESHOLD_MASK)) | (… in _HAL_TSP_VQ_TxConfig()
3359 …REG16_W(&_RegCtrl->VQ1_Config, (REG16_R(&_RegCtrl->VQ1_Config) & (~TSP_VQ1_FORCEFIRE_CNT_1K_MASK))… in _HAL_TSP_VQ_TxConfig()
3362 …REG16_W(&_RegCtrl->VQ2_Config, (REG16_R(&_RegCtrl->VQ2_Config) & (~TSP_VQ2_WR_THRESHOLD_MASK)) | (… in _HAL_TSP_VQ_TxConfig()
3363 …REG16_W(&_RegCtrl->VQ2_Config, (REG16_R(&_RegCtrl->VQ2_Config) & (~TSP_VQ2_FORCEFIRE_CNT_1K_MASK))… in _HAL_TSP_VQ_TxConfig()
3407 REG32_W(&_RegCtrl->VQ0_BASE, (u32BaseAddr >> MIU_BUS)); in HAL_TSP_VQ_Buffer()
3408 REG16_W(&_RegCtrl->VQ0_SIZE, u32VQ_PktNum); in HAL_TSP_VQ_Buffer()
3411 REG32_W(&_RegCtrl->VQ1_Base, (u32BaseAddr >> MIU_BUS)); in HAL_TSP_VQ_Buffer()
3412 REG16_W(&_RegCtrl->VQ1_Size, u32VQ_PktNum); in HAL_TSP_VQ_Buffer()
3415 REG32_W(&_RegCtrl->VQ2_Base, (u32BaseAddr >> MIU_BUS)); in HAL_TSP_VQ_Buffer()
3416 REG16_W(&_RegCtrl->VQ2_Size, u32VQ_PktNum); in HAL_TSP_VQ_Buffer()
3431 REG16_SET(&_RegCtrl->reg160E, TSP_VQTX0_BLOCK_DIS); in HAL_TSP_VQ_Block_Dis()
3434 REG16_SET(&_RegCtrl->reg160E, TSP_VQTX1_BLOCK_DIS); in HAL_TSP_VQ_Block_Dis()
3437 REG16_SET(&_RegCtrl->reg160E, TSP_VQTX2_BLOCK_DIS); in HAL_TSP_VQ_Block_Dis()
3448 REG16_CLR(&_RegCtrl->reg160E, TSP_VQTX0_BLOCK_DIS); in HAL_TSP_VQ_Block_Dis()
3451 REG16_CLR(&_RegCtrl->reg160E, TSP_VQTX1_BLOCK_DIS); in HAL_TSP_VQ_Block_Dis()
3454 REG16_CLR(&_RegCtrl->reg160E, TSP_VQTX2_BLOCK_DIS); in HAL_TSP_VQ_Block_Dis()
3468 REG16_SET(&_RegCtrl->HW2_Config3, TSP_VQ_EN|TSP_VQ2PINGPONG_EN); in HAL_TSP_VQ_Enable()
3472 REG16_CLR(&_RegCtrl->HW2_Config3, TSP_VQ_EN|TSP_VQ2PINGPONG_EN); in HAL_TSP_VQ_Enable()
3482 REG16_SET(&_RegCtrl->VQ0_CTRL, TSP_VQ0_RESET); in HAL_TSP_VQ_Reset()
3485 REG16_SET(&_RegCtrl->VQ1_Config, TSP_VQ1_RESET); in HAL_TSP_VQ_Reset()
3488 REG16_SET(&_RegCtrl->VQ2_Config, TSP_VQ2_RESET); in HAL_TSP_VQ_Reset()
3499 REG16_CLR(&_RegCtrl->VQ0_CTRL, TSP_VQ0_RESET); in HAL_TSP_VQ_Reset()
3502 REG16_CLR(&_RegCtrl->VQ1_Config, TSP_VQ1_RESET); in HAL_TSP_VQ_Reset()
3505 REG16_CLR(&_RegCtrl->VQ2_Config, TSP_VQ2_RESET); in HAL_TSP_VQ_Reset()
3520 REG16_SET(&_RegCtrl->VQ0_CTRL, TSP_VQ0_OVERFLOW_INT_EN); in HAL_TSP_VQ_OverflowInt_En()
3523 REG16_SET(&_RegCtrl->VQ1_Config, TSP_VQ1_OVF_INT_EN); in HAL_TSP_VQ_OverflowInt_En()
3526 REG16_SET(&_RegCtrl->VQ2_Config, TSP_VQ2_OVF_INT_EN); in HAL_TSP_VQ_OverflowInt_En()
3537 REG16_CLR(&_RegCtrl->VQ0_CTRL, TSP_VQ0_OVERFLOW_INT_EN); in HAL_TSP_VQ_OverflowInt_En()
3540 REG16_CLR(&_RegCtrl->VQ1_Config, TSP_VQ1_OVF_INT_EN); in HAL_TSP_VQ_OverflowInt_En()
3543 REG16_CLR(&_RegCtrl->VQ2_Config, TSP_VQ2_OVF_INT_EN); in HAL_TSP_VQ_OverflowInt_En()
3558 REG16_SET(&_RegCtrl->VQ0_CTRL, TSP_VQ0_CLR_OVERFLOW_INT); in HAL_TSP_VQ_OverflowInt_Clr()
3561 REG16_SET(&_RegCtrl->VQ1_Config, TSP_VQ1_CLR_OVF_INT); in HAL_TSP_VQ_OverflowInt_Clr()
3564 REG16_SET(&_RegCtrl->VQ2_Config, TSP_VQ2_CLR_OVF_INT); in HAL_TSP_VQ_OverflowInt_Clr()
3575 REG16_CLR(&_RegCtrl->VQ0_CTRL, TSP_VQ0_CLR_OVERFLOW_INT); in HAL_TSP_VQ_OverflowInt_Clr()
3578 REG16_CLR(&_RegCtrl->VQ1_Config, TSP_VQ1_CLR_OVF_INT); in HAL_TSP_VQ_OverflowInt_Clr()
3581 REG16_CLR(&_RegCtrl->VQ2_Config, TSP_VQ2_CLR_OVF_INT); in HAL_TSP_VQ_OverflowInt_Clr()
3595 REG16_SET(&(_RegCtrl->reg15b8), TSP_PVR1_PINGPONG); in HAL_PVR_Init()
3596 …REG16_W(&(_RegCtrl->FIFO_Src), (REG16_R(&(_RegCtrl->FIFO_Src)) & ~TSP_PVR1_SRC_MASK) | (((MS_U16)p… in HAL_PVR_Init()
3600 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_REG_PINGPONG_EN); in HAL_PVR_Init()
3601 …REG16_W(&(_RegCtrl->FIFO_Src), (REG16_R(&(_RegCtrl->FIFO_Src)) & ~TSP_PVR2_SRC_MASK_L) | ((((MS_U1… in HAL_PVR_Init()
3602 …REG16_W(&(_RegCtrl->PCR_Cfg), (REG16_R(&(_RegCtrl->PCR_Cfg)) & ~TSP_PVR2_SRC_MASK_H) | ((((MS_U16)… in HAL_PVR_Init()
3615 REG16_CLR(&(_RegCtrl->reg15b8), TSP_PVR1_PINGPONG); in HAL_PVR_Exit()
3616 REG16_CLR(&(_RegCtrl->FIFO_Src), TSP_PVR1_SRC_MASK); in HAL_PVR_Exit()
3619 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH); in HAL_PVR_Exit()
3620 REG16_CLR(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH); in HAL_PVR_Exit()
3624 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_REG_PINGPONG_EN); in HAL_PVR_Exit()
3625 REG16_CLR(&(_RegCtrl->FIFO_Src), TSP_PVR2_SRC_MASK_L); in HAL_PVR_Exit()
3626 REG16_CLR(&(_RegCtrl->PCR_Cfg), TSP_PVR2_SRC_MASK_H); in HAL_PVR_Exit()
3629 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR); in HAL_PVR_Exit()
3630 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR); in HAL_PVR_Exit()
3647 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH); in HAL_PVR_Start()
3648 REG16_CLR(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH); in HAL_PVR_Start()
3651 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_ENABLE); in HAL_PVR_Start()
3655 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR); in HAL_PVR_Start()
3656 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR); in HAL_PVR_Start()
3659 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_EN); in HAL_PVR_Start()
3671 REG16_CLR(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_ENABLE); in HAL_PVR_Stop()
3674 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_EN); in HAL_PVR_Stop()
3688 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_PAUSE); in HAL_PVR_Pause()
3691 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_PAUSE); in HAL_PVR_Pause()
3702 REG16_CLR(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_PAUSE); in HAL_PVR_Pause()
3705 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_PAUSE); in HAL_PVR_Pause()
3720 REG16_SET(&(_RegCtrl->reg15b4), TSP_PVR_PID_BYPASS); in HAL_PVR_RecPid()
3721 REG16_CLR(&(_RegCtrl->PVRConfig), TSP_PVR1_REC_ALL_EN); in HAL_PVR_RecPid()
3724 REG16_SET(&(_RegCtrl->reg15b4), TSP_PVR_PID_BYPASS2); in HAL_PVR_RecPid()
3725 REG16_CLR(&(_RegCtrl->PVRConfig), TSP_PVR2_REC_ALL_EN); in HAL_PVR_RecPid()
3736 REG16_CLR(&(_RegCtrl->reg15b4), TSP_PVR_PID_BYPASS); in HAL_PVR_RecPid()
3737 REG16_SET(&(_RegCtrl->PVRConfig), TSP_PVR1_REC_ALL_EN); in HAL_PVR_RecPid()
3740 REG16_CLR(&(_RegCtrl->reg15b4), TSP_PVR_PID_BYPASS2); in HAL_PVR_RecPid()
3741 REG16_SET(&(_RegCtrl->PVRConfig), TSP_PVR2_REC_ALL_EN); in HAL_PVR_RecPid()
3753 REG16_SET(&(_RegCtrl->PVRConfig), TSP_REC_NULL); in HAL_PVR_RecNull()
3757 REG16_CLR(&(_RegCtrl->PVRConfig), TSP_REC_NULL); in HAL_PVR_RecNull()
3770 REG32_W(&_RegCtrl->TsRec_Head, (u32StartAddr0>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
3772 REG32_W(&(_RegCtrl->TsRec_Tail), (u32EndAddr0 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
3774 … REG32_W(&(_RegCtrl->TsRec_Mid_PVR1_WPTR), (u32StartAddr0>>MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
3777 … REG32_W(&_RegCtrl->Str2mi_head2pvr1, (u32StartAddr1>> MIU_BUS) & TSP_HW_PVR1_BUF_HEAD2_MASK); in HAL_PVR_SetBuf()
3779 … REG32_W(&(_RegCtrl->Str2mi_tail2pvr1), (u32EndAddr1 >> MIU_BUS) &TSP_HW_PVR1_BUF_TAIL2_MASK); in HAL_PVR_SetBuf()
3781 … REG32_W(&(_RegCtrl->Str2mi_mid2pvr1), (u32StartAddr1>>MIU_BUS) & TSP_HW_PVR1_BUF_MID2_MASK); in HAL_PVR_SetBuf()
3785 … REG32_W(&_RegCtrl->Str2mi_head1_pvr2, (u32StartAddr0>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
3787 REG32_W(&_RegCtrl->Str2mi_tail1_pvr2, (u32EndAddr0>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
3789 … REG32_W(&(_RegCtrl->Str2mi_mid1_wptr_pvr2), (u32StartAddr0>>MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
3792 … REG32_W(&_RegCtrl->Str2mi_head2_pvr2, (u32StartAddr1>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
3794 REG32_W(&_RegCtrl->Str2mi_tail2_pvr2, (u32EndAddr1>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
3796 … REG32_W(&(_RegCtrl->Str2mi_mid2_pvr2), (u32StartAddr1>>MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
3810 REG32_W(&_RegCtrl->TsRec_Head, (u32StartAddr0>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_StartAddr()
3813 … REG32_W(&_RegCtrl->Str2mi_head2pvr1, (u32StartAddr1>> MIU_BUS) & TSP_HW_PVR1_BUF_HEAD2_MASK); in HAL_PVR_SetStr2Miu_StartAddr()
3817 … REG32_W(&_RegCtrl->Str2mi_head1_pvr2, (u32StartAddr0>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_StartAddr()
3820 … REG32_W(&_RegCtrl->Str2mi_head2_pvr2, (u32StartAddr1>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_StartAddr()
3834 REG32_W(&(_RegCtrl->TsRec_Mid_PVR1_WPTR), (u32MidAddr0>>4) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_MidAddr()
3837 REG32_W(&(_RegCtrl->Str2mi_mid2pvr1), (u32MidAddr1>>4) & TSP_HW_PVR1_BUF_MID2_MASK); in HAL_PVR_SetStr2Miu_MidAddr()
3841 REG32_W(&(_RegCtrl->Str2mi_mid1_wptr_pvr2), (u32MidAddr0>>4) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_MidAddr()
3844 REG32_W(&(_RegCtrl->Str2mi_mid2_pvr2), (u32MidAddr1>>4) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_MidAddr()
3857 REG32_W(&(_RegCtrl->TsRec_Tail), (u32EndAddr0 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_EndAddr()
3860 … REG32_W(&(_RegCtrl->Str2mi_tail2pvr1), (u32EndAddr1 >> MIU_BUS) &TSP_HW_PVR1_BUF_TAIL2_MASK); in HAL_PVR_SetStr2Miu_EndAddr()
3864 REG32_W(&_RegCtrl->Str2mi_tail1_pvr2, (u32EndAddr0>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_EndAddr()
3867 REG32_W(&_RegCtrl->Str2mi_tail2_pvr2, (u32EndAddr1>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_EndAddr()
3879 return (REG32_R(&_RegCtrl->TsRec_Mid_PVR1_WPTR) << MIU_BUS); in HAL_PVR_GetWritePtr()
3882 return (REG32_R(&_RegCtrl->Str2mi_mid1_wptr_pvr2) << MIU_BUS); in HAL_PVR_GetWritePtr()
3899 *eSrc = ((REG16_R(&(_RegCtrl->FIFO_Src)) & TSP_PVR1_SRC_MASK) >> TSP_PVR1_SRC_SHIFT); in HAL_PVR_GetEngSrc()
3903 … u16Value = (REG16_R(&(_RegCtrl->FIFO_Src)) & TSP_PVR2_SRC_MASK_L)>> TSP_PVR2_SRC_SHIFT_L; in HAL_PVR_GetEngSrc()
3904 u16Value |= ((REG16_R(&(_RegCtrl->PCR_Cfg)) & TSP_PVR2_SRC_MASK_H) << 1); in HAL_PVR_GetEngSrc()
4116 REG16_SET(&_RegCtrl->reg160C, TSP_RECORD192_EN); in HAL_PVR_SetStrPacketMode()
4119 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_PKT192_EN); in HAL_PVR_SetStrPacketMode()
4130 REG16_CLR(&_RegCtrl->reg160C, TSP_RECORD192_EN); in HAL_PVR_SetStrPacketMode()
4133 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_PKT192_EN); in HAL_PVR_SetStrPacketMode()
4147 REG16_CLR(&_RegCtrl->reg160C, TSP_PVR1_LPCR1_RLD); in HAL_PVR_GetPVRTimeStamp()
4149 u32lpcr = REG32_R(&_RegCtrl->PVR1_LPcr1); in HAL_PVR_GetPVRTimeStamp()
4151 REG16_SET(&_RegCtrl->reg160C, TSP_PVR1_LPCR1_RLD); in HAL_PVR_GetPVRTimeStamp()
4155 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_RLD); in HAL_PVR_GetPVRTimeStamp()
4157 u32lpcr = REG32_R(&_RegCtrl->PVR2_LPCR1); in HAL_PVR_GetPVRTimeStamp()
4159 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_RLD); in HAL_PVR_GetPVRTimeStamp()
4172 REG16_SET(&_RegCtrl->reg160C, TSP_PVR1_LPCR1_WLD); in HAL_PVR_SetPVRTimeStamp()
4174 REG32_W(&_RegCtrl->PVR1_LPcr1, u32Stamp); in HAL_PVR_SetPVRTimeStamp()
4176 REG16_CLR(&_RegCtrl->reg160C, TSP_PVR1_LPCR1_WLD); in HAL_PVR_SetPVRTimeStamp()
4179 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_WLD); in HAL_PVR_SetPVRTimeStamp()
4181 REG32_W(&_RegCtrl->PVR2_LPCR1, u32Stamp); in HAL_PVR_SetPVRTimeStamp()
4183 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_WLD); in HAL_PVR_SetPVRTimeStamp()
4220 REG16_SET(&_RegCtrl->HW2_Config3, TSP_PVR1_ALIGN_EN); in HAL_PVR_Alignment_Enable()
4223 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_PVR_ALIGN_EN); in HAL_PVR_Alignment_Enable()
4234 REG16_CLR(&_RegCtrl->HW2_Config3, TSP_PVR1_ALIGN_EN); in HAL_PVR_Alignment_Enable()
4237 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_PVR_ALIGN_EN); in HAL_PVR_Alignment_Enable()
4302 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR1_BLOCK_DIS); in HAL_PVR_Block_Dis()
4305 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_BLOCK_DIS); in HAL_PVR_Block_Dis()
4316 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR1_BLOCK_DIS); in HAL_PVR_Block_Dis()
4319 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_BLOCK_DIS); in HAL_PVR_Block_Dis()
4333 … REG16_MSK_W(&_RegCtrl->reg15b8, TSP_BURST_LEN_MASK, (u16BurstMode << TSP_BURST_LEN_SHIFT)); in HAL_PVR_BurstLen()
4336 …REG32_MSK_W(&_RegCtrl->PVR2_Config, TSP_PVR2_BURST_LEN_MASK, (u16BurstMode << TSP_PVR2_BURST_LEN_S… in HAL_PVR_BurstLen()
4424 REG16_W(&_RegCtrl->MOBF_PVR1_Index[0], (u32Key & TSP_MOBF_PVR1_INDEX_MASK)); in HAL_PVR_MOBF_Enable()
4427 REG16_W(&_RegCtrl->MOBF_PVR2_Index[0], (u32Key & TSP_MOBF_PVR2_INDEX_MASK)); in HAL_PVR_MOBF_Enable()
4499 REG32_W(&_RegCtrl->MCU_Data0, INFO_FW_VERSION); in HAL_TSP_HCMD_GetInfo()
4502 REG32_W(&_RegCtrl->MCU_Data0, INFO_FW_DATE); in HAL_TSP_HCMD_GetInfo()
4505 REG32_W(&_RegCtrl->MCU_Data0, INFO_FW_VERSION); in HAL_TSP_HCMD_GetInfo()
4510 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_INFO); in HAL_TSP_HCMD_GetInfo()
4513 u32Data = REG32_R(&_RegCtrl->MCU_Data1); in HAL_TSP_HCMD_GetInfo()
4514 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear in HAL_TSP_HCMD_GetInfo()
4523 REG32_W(&_RegCtrl->MCU_Data0 , u32Value); in HAL_TSP_HCMD_BufRst()
4524 REG32_W(&_RegCtrl->MCU_Cmd , TSP_MCU_CMD_BUFRST); in HAL_TSP_HCMD_BufRst()
4534 REG32_W(&_RegCtrl->MCU_Data0, u32Addr); in HAL_TSP_HCMD_Read()
4535 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_READ); in HAL_TSP_HCMD_Read()
4538 u32Data = REG32_R(&_RegCtrl->MCU_Data1); in HAL_TSP_HCMD_Read()
4539 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear in HAL_TSP_HCMD_Read()
4549 REG32_W(&_RegCtrl->MCU_Data0, u32Addr); in HAL_TSP_HCMD_Write()
4550 REG32_W(&_RegCtrl->MCU_Data1, u32Value); in HAL_TSP_HCMD_Write()
4551 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_WRITE); in HAL_TSP_HCMD_Write()
4554 u32Data = REG32_R(&_RegCtrl->MCU_Data1); in HAL_TSP_HCMD_Write()
4555 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear in HAL_TSP_HCMD_Write()
4565 REG32_W(&_RegCtrl->MCU_Data1, 0); in HAL_TSP_HCMD_Alive()
4566 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_ALIVE); //@TODO check FW HCMD in HAL_TSP_HCMD_Alive()
4568 u32Data = REG32_R(&_RegCtrl->MCU_Data1); in HAL_TSP_HCMD_Alive()
4569 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear in HAL_TSP_HCMD_Alive()
4576 REG32_W(&_RegCtrl->MCU_Data0, mcu_data0); in HAL_TSP_HCMD_SET()
4577 REG32_W(&_RegCtrl->MCU_Data1, mcu_data1); in HAL_TSP_HCMD_SET()
4578 REG32_W(&_RegCtrl->MCU_Cmd, mcu_cmd); in HAL_TSP_HCMD_SET()
4583 *pmcu_cmd = REG32_R(&_RegCtrl->MCU_Cmd); in HAL_TSP_HCMD_GET()
4584 *pmcu_data0 = REG32_R(&_RegCtrl->MCU_Data0); in HAL_TSP_HCMD_GET()
4585 *pmcu_data1 = REG32_R(&_RegCtrl->MCU_Data1); in HAL_TSP_HCMD_GET()
4592 REG32_W(&_RegCtrl->MCU_Data0, FltId); in HAL_TSP_HCMD_SecRdyInt_Disable()
4593 REG32_W(&_RegCtrl->MCU_Data1,u32Data); in HAL_TSP_HCMD_SecRdyInt_Disable()
4594 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_SECRDYINT_DISABLE); // @TODO add HCMD list here in HAL_TSP_HCMD_SecRdyInt_Disable()
4596 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear in HAL_TSP_HCMD_SecRdyInt_Disable()
4605 REG32_W(&_RegCtrl->MCU_Data0, u32Enable); in HAL_TSP_HCMD_Dbg()
4606 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_DBG); in HAL_TSP_HCMD_Dbg()
4609 u32Data = REG32_R(&_RegCtrl->MCU_Data1); in HAL_TSP_HCMD_Dbg()
4610 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear in HAL_TSP_HCMD_Dbg()
4612 return REG32_R(&_RegCtrl->MCU_Data1); in HAL_TSP_HCMD_Dbg()
4617 REG16_CLR(&_RegCtrl->PKT_CNT, TSP_DBG_SEL_MASK); in HAL_TSP_GetDBGStatus()
4618 REG16_SET(&_RegCtrl->PKT_CNT, ((u16Sel << TSP_DBG_SEL_SHIFT) & TSP_DBG_SEL_MASK)); in HAL_TSP_GetDBGStatus()
4620 return REG32_R(&_RegCtrl->TSP_Debug); in HAL_TSP_GetDBGStatus()
4636 REG16_SET(&_RegCtrl->HwInt_Stat, TSP_INT_EN_MASK & u32Mask); in HAL_TSP_INT_Enable()
4648 …REG16_SET(&_RegCtrl->SwInt_Stat1_L, (TSP_HWINT2_EN_MASK & (u32Mask >> 8)) | TSP_HWINT2_STATUS_MASK… in HAL_TSP_INT_Enable()
4654 REG16_CLR(&_RegCtrl->HwInt_Stat, TSP_INT_EN_MASK & u32Mask); in HAL_TSP_INT_Disable()
4656 REG16_W(&_RegCtrl->SwInt_Stat1_L, in HAL_TSP_INT_Disable()
4657 (REG16_R(&_RegCtrl->SwInt_Stat1_L) & ~(TSP_HWINT2_EN_MASK & (u32Mask >> 8))) | in HAL_TSP_INT_Disable()
4664 REG16_CLR(&_RegCtrl->HwInt_Stat, (u32Mask & 0x00FF) << 8); in HAL_TSP_INT_ClrHW()
4666 REG16_W(&_RegCtrl->SwInt_Stat1_L, in HAL_TSP_INT_ClrHW()
4667 (REG16_R(&_RegCtrl->SwInt_Stat1_L) & (~TSP_HWINT2_STATUS_MASK)) | in HAL_TSP_INT_ClrHW()
4676 …status = (MS_U32)(((REG16_R(&_RegCtrl->SwInt_Stat1_L) & TSP_HWINT2_STATUS_MASK) >> TSP_HWINT2_STAT… in HAL_TSP_INT_GetHW()
4678 …status |= (MS_U32)((REG16_R(&_RegCtrl->HwInt_Stat) & TSP_HWINT_STATUS_MASK) >> TSP_HWINT_STATUS_SH… in HAL_TSP_INT_GetHW()
4686 REG32_W(&_RegCtrl->SwInt_Stat, 0); in HAL_TSP_INT_ClrSW()
4692 return REG32_R(&_RegCtrl->SwInt_Stat); in HAL_TSP_INT_GetSW()
5011 …*pbExtSync = ((REG16_R(&_RegCtrl->Hw_Config0) & TSP_HW_CFG0_TSIF0_EXTSYNC) == TSP_HW_CFG0_TSIF0_EX… in HAL_TSP_GetTSIF_Status()
5012 … *pbParl = ((REG16_R(&_RegCtrl->Hw_Config0) & TSP_HW_CFG0_TSIF0_PARL) == TSP_HW_CFG0_TSIF0_PARL); in HAL_TSP_GetTSIF_Status()
5022 …*pbExtSync = ((REG16_R(&_RegCtrl->Hw_Config2) & TSP_HW_CFG2_TSIF1_EXTSYNC) == TSP_HW_CFG2_TSIF1_EX… in HAL_TSP_GetTSIF_Status()
5023 … *pbParl = ((REG16_R(&_RegCtrl->Hw_Config2) & TSP_HW_CFG2_TSIF1_PARL) == TSP_HW_CFG2_TSIF1_PARL); in HAL_TSP_GetTSIF_Status()
5033 … *pbExtSync = ((REG32_R(&_RegCtrl->PVR2_Config) & TSP_EXT_SYNC_SEL2) == TSP_EXT_SYNC_SEL2); in HAL_TSP_GetTSIF_Status()
5034 *pbParl = ((REG32_R(&_RegCtrl->PVR2_Config) & TSP_P_SEL2) == TSP_P_SEL2); in HAL_TSP_GetTSIF_Status()
5047 REG16_SET(&_RegCtrl->reg15b8, TSP_REMOVE_DUP_AV_PKT); in HAL_TSP_PktDmx_RmDupAVPkt()
5051 REG16_CLR(&_RegCtrl->reg15b8, TSP_REMOVE_DUP_AV_PKT); in HAL_TSP_PktDmx_RmDupAVPkt()
5062 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_APES_ERR_RM_EN); in HAL_TSP_TEI_RemoveErrorPkt()
5065 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_VPES_ERR_RM_EN); in HAL_TSP_TEI_RemoveErrorPkt()
5076 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_APES_ERR_RM_EN); in HAL_TSP_TEI_RemoveErrorPkt()
5079 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_VPES_ERR_RM_EN); in HAL_TSP_TEI_RemoveErrorPkt()
5094 REG16_SET(&_RegCtrl->reg15b8, TSP_TEI_SKIPE_PKT_PID0); in HAL_TSP_TEI_SKIP()
5097 REG16_SET(&_RegCtrl->reg15b8, TSP_TEI_SKIPE_PKT_PID1); in HAL_TSP_TEI_SKIP()
5100 REG32_SET(&_RegCtrl->PVR2_Config, TSP_TEI_SKIP_PKT2); in HAL_TSP_TEI_SKIP()
5111 REG16_CLR(&_RegCtrl->reg15b8, TSP_TEI_SKIPE_PKT_PID0); in HAL_TSP_TEI_SKIP()
5114 REG16_CLR(&_RegCtrl->reg15b8, TSP_TEI_SKIPE_PKT_PID1); in HAL_TSP_TEI_SKIP()
5117 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_TEI_SKIP_PKT2); in HAL_TSP_TEI_SKIP()
5171 REG16_SET(&_RegCtrl->reg160C,TSP_ORZ_DMAW_PROT_EN); in HAL_TSP_OR_Address_Protect_En()
5175 REG16_CLR(&_RegCtrl->reg160C,TSP_ORZ_DMAW_PROT_EN); in HAL_TSP_OR_Address_Protect_En()
5183 …REG32_W(&_RegCtrl->ORZ_DMAW_LBND,(MS_U32)(((u32AddrL - phyMiuOffset) >> MIU_BUS) & TSP_ORZ_DMAW_LB… in HAL_TSP_OR_Address_Protect()
5184 …REG32_W(&_RegCtrl->ORZ_DMAW_UBND,(MS_U32)(((u32AddrH - phyMiuOffset) >> MIU_BUS) & TSP_ORZ_DMAW_UB… in HAL_TSP_OR_Address_Protect()
5192 REG16_SET(&_RegCtrl->reg15b4,TSP_SEC_CB_PVR2_DAMW_PROTECT_EN); in HAL_TSP_SEC_Address_Protect_En()
5196 REG16_CLR(&_RegCtrl->reg15b4,TSP_SEC_CB_PVR2_DAMW_PROTECT_EN); in HAL_TSP_SEC_Address_Protect_En()
5209 REG32_W(&_RegCtrl->DMAW_LBND0,u32LBnd); in HAL_TSP_SEC_Address_Protect()
5210 REG32_W(&_RegCtrl->DMAW_UBND0,u32UBnd); in HAL_TSP_SEC_Address_Protect()
5213 REG32_W(&_RegCtrl->DMAW_LBND1,u32LBnd); in HAL_TSP_SEC_Address_Protect()
5214 REG32_W(&_RegCtrl->DMAW_UBND1,u32UBnd); in HAL_TSP_SEC_Address_Protect()
5262 REG32_W(&_RegCtrl->DMAW_LBND2, u32LBnd); in HAL_TSP_PVR_Address_Protect()
5263 REG32_W(&_RegCtrl->DMAW_UBND2, u32UBnd); in HAL_TSP_PVR_Address_Protect()
5266 REG32_W(&_RegCtrl->DMAW_LBND3, u32LBnd); in HAL_TSP_PVR_Address_Protect()
5267 REG32_W(&_RegCtrl->DMAW_UBND3, u32UBnd); in HAL_TSP_PVR_Address_Protect()
5547 u16PktDmxSrc = _CLR_(REG16_R(&_RegCtrl->reg15b8), TSP_MATCH_PID_SRC_MASK); in HAL_DSCMB_GetStatus()
5567 REG16_W(&_RegCtrl->reg15b8, u16PktDmxSrc); in HAL_DSCMB_GetStatus()
5569 …REG16_W(&_RegCtrl->PVRConfig, _SET_(REG16_R(&_RegCtrl->PVRConfig), TSP_MATCH_PID_LD)); // Set 1 to… in HAL_DSCMB_GetStatus()
5572 REG16_W(&_RegCtrl->PVRConfig, _CLR_(REG16_R(&_RegCtrl->PVRConfig), TSP_MATCH_PID_LD)); // freeze in HAL_DSCMB_GetStatus()
5574 u16WordId = _CLR_(REG16_R(&_RegCtrl->PVRConfig), TSP_MATCH_PID_SEL_MASK); in HAL_DSCMB_GetStatus()
5579 REG16_MSK_W(&_RegCtrl->PVRConfig,TSP_MATCH_PID_SEL_MASK,u16WordId); in HAL_DSCMB_GetStatus()
5586 *pu32ScmbSts = _AND_(REG32_R(&_RegCtrl->TsPidScmbStatTsin), u32PIDFltMask); in HAL_DSCMB_GetStatus()
5588 …REG16_W(&_RegCtrl->PVRConfig, _SET_(REG16_R(&_RegCtrl->PVRConfig), TSP_MATCH_PID_LD)); // re-enable in HAL_DSCMB_GetStatus()