Lines Matching refs:TSP_Ctrl1

261     REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_STANDBY);  in HAL_TSP_HwPatch()
345         REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_PVR_CMD_QUEUE_ENABLE);  in HAL_TSP_Reset()
350         REG16_SET(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_CMDQ_RESET);  in HAL_TSP_Reset()
363         REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_CMDQ_RESET);  in HAL_TSP_Reset()
945 …REG16_SET(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_PVR_CMD_QUEUE_ENABLE);    // for wishbone DMA (load firm…  in HAL_TSP_TSIF_FileEn()
970                 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_PVR_CMD_QUEUE_ENABLE);  in HAL_TSP_TSIF_FileEn()
1573             REG16_SET(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_FILEIN_PAUSE);  in HAL_TSP_File_Pause()
1591             REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_FILEIN_PAUSE);  in HAL_TSP_File_Resume()
1667                 REG16_SET(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_CMDQ_RESET);  in HAL_TSP_Filein_CmdQRst()
1684                 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_CMDQ_RESET);  in HAL_TSP_Filein_CmdQRst()
1820             if (REG16_R(&_RegCtrl->TSP_Ctrl1) & TSP_CTRL1_FILEIN_PAUSE )  in HAL_TSP_Filein_GetState()