Lines Matching refs:MDrv_WriteByte

257     MDrv_WriteByte(u32RegAddr, u8Flag);  in MDrv_DDC2BI_Set_INT_FLAG()
262     MDrv_WriteByte(u32RegAddr, 0x00);  in MDrv_DDC2BI_Set_INT_FLAG()
269     MDrv_WriteByte(DDC2BI_ADC_INT_MASK, u8Mask);  in MDrv_DDC2BI_Set_INT_Mask()
276     MDrv_WriteByte(DDC2BI_ADC_RB_WP, u8Data);  in MDrv_DDC2BI_Write_Buf()
603     MDrv_WriteByte(DDC2BI_ADC_ID, 0xB7);  in MDrv_DDC2BI_Init()
622     MDrv_WriteByte(DDC2BI_CTRL, 0x00);  in MDrv_DDC2BI_Init()
627     MDrv_WriteByte(DDC2BI_ADC_INT_MASK, 0x67);  // enable read and write status interrupt  in MDrv_DDC2BI_Init()
638     MDrv_WriteByte(DDC2BI_DVI0_INT_MASK, 0x67);  // enable read and write status interrupt  in MDrv_DDC2BI_Init()
639     MDrv_WriteByte(DDC2BI_DVI1_INT_MASK, 0x67);  // enable read and write status interrupt  in MDrv_DDC2BI_Init()
640     MDrv_WriteByte(DDC2BI_DVI2_INT_MASK, 0x67);  // enable read and write status interrupt  in MDrv_DDC2BI_Init()
641     MDrv_WriteByte(DDC2BI_DVI3_INT_MASK, 0x67);  // enable read and write status interrupt  in MDrv_DDC2BI_Init()
655     MDrv_WriteByte(DDC2BI_ADC_INT_MASK, 0xFF);  in MDrv_DDC2BI_Exit()
656     MDrv_WriteByte(DDC2BI_DVI0_INT_MASK, 0xFF);  in MDrv_DDC2BI_Exit()
657     MDrv_WriteByte(DDC2BI_DVI1_INT_MASK, 0xFF);  in MDrv_DDC2BI_Exit()
658     MDrv_WriteByte(DDC2BI_DVI2_INT_MASK, 0xFF);  in MDrv_DDC2BI_Exit()
659     MDrv_WriteByte(DDC2BI_DVI3_INT_MASK, 0xFF);  in MDrv_DDC2BI_Exit()