355 static MPP_RET set_roi_pos_val(RK_U32 *buf, RK_U32 pos, RK_U32 value)  in set_roi_pos_val()  argument
360     buf[index] = buf[index] | (value << bits);  in set_roi_pos_val()
364 #define set_roi_qpadj(buf, index, val) \  argument
367         set_roi_pos_val(buf, offset, val); \
370 #define set_roi_force_split(buf, index, val) \  argument
373         set_roi_pos_val(buf, offset, val); \
376 #define set_roi_force_intra(buf, index, val) \  argument
379         set_roi_pos_val(buf, offset, val); \
382 #define set_roi_force_inter(buf, index, val) \  argument
385         set_roi_pos_val(buf, offset, val); \
388 static void set_roi_cu8_base_cfg(RK_U32 *buf, RK_U32 index, Vepu580RoiH265BsCfg val)  in set_roi_cu8_base_cfg()  argument
390     set_roi_qpadj(buf, index, val.qp_adj);  in set_roi_cu8_base_cfg()
391     set_roi_force_split(buf, index, val.force_split);  in set_roi_cu8_base_cfg()
392     set_roi_force_intra(buf, index, val.force_intra);  in set_roi_cu8_base_cfg()
393     set_roi_force_inter(buf, index, val.force_inter);  in set_roi_cu8_base_cfg()
396 static void set_roi_cu16_base_cfg(RK_U32 *buf, RK_U32 index, Vepu580RoiH265BsCfg val)  in set_roi_cu16_base_cfg()  argument
399     set_roi_qpadj(buf, index, val.qp_adj);  in set_roi_cu16_base_cfg()
400     set_roi_force_split(buf, index, val.force_split);  in set_roi_cu16_base_cfg()
401     set_roi_force_intra(buf, index, val.force_intra);  in set_roi_cu16_base_cfg()
402     set_roi_force_inter(buf, index, val.force_inter);  in set_roi_cu16_base_cfg()
405 static void set_roi_cu32_base_cfg(RK_U32 *buf, RK_U32 index, Vepu580RoiH265BsCfg val)  in set_roi_cu32_base_cfg()  argument
408     set_roi_qpadj(buf, index, val.qp_adj);  in set_roi_cu32_base_cfg()
409     set_roi_force_split(buf, index, val.force_split);  in set_roi_cu32_base_cfg()
410     set_roi_force_intra(buf, index, val.force_intra);  in set_roi_cu32_base_cfg()
411     set_roi_force_inter(buf, index, val.force_inter);  in set_roi_cu32_base_cfg()
414 static void set_roi_cu64_base_cfg(RK_U32 *buf, Vepu580RoiH265BsCfg val)  in set_roi_cu64_base_cfg()  argument
416     set_roi_qpadj(buf, 84, val.qp_adj);  in set_roi_cu64_base_cfg()
417     set_roi_force_split(buf, 84, val.force_split);  in set_roi_cu64_base_cfg()
418     set_roi_force_intra(buf, 84, val.force_intra);  in set_roi_cu64_base_cfg()
419     set_roi_force_inter(buf, 84, val.force_inter);  in set_roi_cu64_base_cfg()
422 static void set_roi_qp_cfg(void *buf, RK_U32 index, Vepu541RoiCfg *cfg)  in set_roi_qp_cfg()  argument
424     Vepu580RoiQpCfg *qp_cfg_base = (Vepu580RoiQpCfg *)buf;  in set_roi_qp_cfg()
432 #define set_roi_cu8_qp_cfg(buf, index, cfg) \  argument
435         set_roi_qp_cfg(buf, offset, cfg); \
438 #define set_roi_cu16_qp_cfg(buf, index, cfg) \  argument
441         set_roi_qp_cfg(buf, offset, cfg); \
444 #define set_roi_cu32_qp_cfg(buf, index, cfg) \  argument
447         set_roi_qp_cfg(buf, offset, cfg); \
450 #define set_roi_cu64_qp_cfg(buf, cfg) \  argument
453         set_roi_qp_cfg(buf, offset, cfg); \
456 void set_roi_amv(RK_U32 *buf, Vepu580RoiH265BsCfg val)  in set_roi_amv()  argument
458     set_roi_pos_val(buf, 511, val.amv_en);  in set_roi_amv()
512 void set_roi_cu16_split_cu8(RK_U32 *buf, RK_U32 cu16index, Vepu580RoiH265BsCfg val)  in set_roi_cu16_split_cu8()  argument
529         set_roi_cu8_base_cfg(buf, zindex, val);  in set_roi_cu16_split_cu8()