322         pic_vir_src_ystride = src_params->src_width_vir * 3 / 4;  in set_hist_to_vdpp2_reg()
324         pic_vir_src_ystride = src_params->src_width_vir * 4 / 4;  in set_hist_to_vdpp2_reg()
326         pic_vir_src_ystride = src_params->src_width_vir * 10 / 8 / 4;  in set_hist_to_vdpp2_reg()
328         pic_vir_src_ystride = src_params->src_width_vir / 4;  in set_hist_to_vdpp2_reg()
339         (src_params->src_width_vir > VDPP2_HIST_HSD_DISABLE_LIMIT)) {  in set_hist_to_vdpp2_reg()
341                   src_params->src_width_vir, dci_hsd_mode);  in set_hist_to_vdpp2_reg()
1131         dst_reg->common.reg12.sw_vdpp_src_vir_y_stride = src_params->src_width_vir / 4;  in vdpp2_params_to_reg()
1522         if (!ctx->params.src_width_vir)  in vdpp2_set_param()
1523             ctx->params.src_width_vir = MPP_ALIGN(ctx->params.src_width, 16);  in vdpp2_set_param()
1572         ctx->params.src_width_vir = param->com2.src_width_vir;  in vdpp2_set_param()
1628         params->src_width_vir < params->src_width) {  in check_cap()
1631                   params->src_width_vir, params->src_height_vir);  in check_cap()
1642         (params->src_width_vir > VDPP2_VEP_MAX_WIDTH) ||  in check_cap()
1646         (params->src_width_vir < VDPP2_MODE_MIN_WIDTH)) {  in check_cap()
1649                   params->src_width_vir, params->src_height_vir);  in check_cap()
1667     if ((params->src_width_vir & 0xf) || (params->dst_width_vir & 0xf)) {  in check_cap()
1670                   params->src_width_vir, params->dst_width_vir);  in check_cap()
1730         (params->src_width_vir > VDPP2_HIST_MAX_WIDTH) ||  in check_cap()
1735                   params->src_width_vir, params->src_height_vir);  in check_cap()
1743         if (params->src_width_vir & 0xf) {  in check_cap()
1748         if (params->src_width_vir & 0x3) {  in check_cap()
1755               params->src_width, params->src_width_vir,  in check_cap()