415     dst_reg->dci.reg4.sw_dci_hist_addr = src_params->hist;  in set_hist_to_vdpp2_reg()
450     dst_reg->es.reg4.diff_gain0 = p_es_param->es_iK1;  in set_es_to_vdpp2_reg()
451     dst_reg->es.reg4.diff_limit = p_es_param->es_iDeltaLimit;  in set_es_to_vdpp2_reg()
824     dst_reg->sharp.reg4.sw_peaking_h00  = p_shp_param->peaking_filt_core_H0[0];  in set_shp_to_vdpp2_reg()
825     dst_reg->sharp.reg4.sw_peaking_h01  = p_shp_param->peaking_filt_core_H0[1];  in set_shp_to_vdpp2_reg()
826     dst_reg->sharp.reg4.sw_peaking_h02  = p_shp_param->peaking_filt_core_H0[2];  in set_shp_to_vdpp2_reg()
1106     dst_reg->common.reg4.sw_vdpp_clk_on = 1;  in vdpp2_params_to_reg()
1107     dst_reg->common.reg4.sw_md_clk_on = 1;  in vdpp2_params_to_reg()
1108     dst_reg->common.reg4.sw_dect_clk_on = 1;  in vdpp2_params_to_reg()
1109     dst_reg->common.reg4.sw_me_clk_on = 1;  in vdpp2_params_to_reg()
1110     dst_reg->common.reg4.sw_mc_clk_on = 1;  in vdpp2_params_to_reg()
1111     dst_reg->common.reg4.sw_eedi_clk_on = 1;  in vdpp2_params_to_reg()
1112     dst_reg->common.reg4.sw_ble_clk_on = 1;  in vdpp2_params_to_reg()
1113     dst_reg->common.reg4.sw_out_clk_on = 1;  in vdpp2_params_to_reg()
1114     dst_reg->common.reg4.sw_ctrl_clk_on = 1;  in vdpp2_params_to_reg()
1115     dst_reg->common.reg4.sw_ram_clk_on = 1;  in vdpp2_params_to_reg()
1116     dst_reg->common.reg4.sw_dma_clk_on = 1;  in vdpp2_params_to_reg()
1117     dst_reg->common.reg4.sw_reg_clk_on = 1;  in vdpp2_params_to_reg()