Lines Matching refs:ctx
35 static void vdpu2_mpg4d_setup_regs_by_syntax(hal_mpg4_ctx *ctx, MppSyntax syntax) in vdpu2_mpg4d_setup_regs_by_syntax() argument
37 M4vdVdpu2Regs_t *regs = ctx->regs; in vdpu2_mpg4d_setup_regs_by_syntax()
41 RK_S32 mv_buf_fd = mpp_buffer_get_fd(ctx->mv_buf); in vdpu2_mpg4d_setup_regs_by_syntax()
58 ctx->bitstrm_len = stream_length; in vdpu2_mpg4d_setup_regs_by_syntax()
73 RK_U8 *dst = (RK_U8 *)mpp_buffer_get_ptr(ctx->qp_table); in vdpu2_mpg4d_setup_regs_by_syntax()
123 mpp_dev_set_reg_offset(ctx->dev, 64, consumed_bytes_align); in vdpu2_mpg4d_setup_regs_by_syntax()
143 mpp_assert(ctx->fd_ref1 >= 0); in vdpu2_mpg4d_setup_regs_by_syntax()
144 if (ctx->fd_ref1 >= 0) { in vdpu2_mpg4d_setup_regs_by_syntax()
145 regs->reg131_ref0_base = (RK_U32)ctx->fd_ref1; in vdpu2_mpg4d_setup_regs_by_syntax()
146 regs->reg148_ref1_base = (RK_U32)ctx->fd_ref1; in vdpu2_mpg4d_setup_regs_by_syntax()
148 regs->reg131_ref0_base = (RK_U32)ctx->fd_curr; in vdpu2_mpg4d_setup_regs_by_syntax()
149 regs->reg148_ref1_base = (RK_U32)ctx->fd_curr; in vdpu2_mpg4d_setup_regs_by_syntax()
152 mpp_assert(ctx->fd_ref0 >= 0); in vdpu2_mpg4d_setup_regs_by_syntax()
153 if (ctx->fd_ref0 >= 0) { in vdpu2_mpg4d_setup_regs_by_syntax()
154 regs->reg134_ref2_base = (RK_U32)ctx->fd_ref0; in vdpu2_mpg4d_setup_regs_by_syntax()
155 regs->reg135_ref3_base = (RK_U32)ctx->fd_ref0; in vdpu2_mpg4d_setup_regs_by_syntax()
157 regs->reg134_ref2_base = (RK_U32)ctx->fd_curr; in vdpu2_mpg4d_setup_regs_by_syntax()
158 regs->reg135_ref3_base = (RK_U32)ctx->fd_curr; in vdpu2_mpg4d_setup_regs_by_syntax()
175 if (ctx->fd_ref0 >= 0) { in vdpu2_mpg4d_setup_regs_by_syntax()
176 regs->reg131_ref0_base = (RK_U32)ctx->fd_ref0; in vdpu2_mpg4d_setup_regs_by_syntax()
177 regs->reg148_ref1_base = (RK_U32)ctx->fd_ref0; in vdpu2_mpg4d_setup_regs_by_syntax()
179 regs->reg131_ref0_base = (RK_U32)ctx->fd_curr; in vdpu2_mpg4d_setup_regs_by_syntax()
180 regs->reg148_ref1_base = (RK_U32)ctx->fd_curr; in vdpu2_mpg4d_setup_regs_by_syntax()
182 regs->reg134_ref2_base = (RK_U32)ctx->fd_curr; in vdpu2_mpg4d_setup_regs_by_syntax()
183 regs->reg135_ref3_base = (RK_U32)ctx->fd_curr; in vdpu2_mpg4d_setup_regs_by_syntax()
194 regs->reg131_ref0_base = (RK_U32)ctx->fd_curr; in vdpu2_mpg4d_setup_regs_by_syntax()
195 regs->reg148_ref1_base = (RK_U32)ctx->fd_curr; in vdpu2_mpg4d_setup_regs_by_syntax()
196 regs->reg134_ref2_base = (RK_U32)ctx->fd_curr; in vdpu2_mpg4d_setup_regs_by_syntax()
197 regs->reg135_ref3_base = (RK_U32)ctx->fd_curr; in vdpu2_mpg4d_setup_regs_by_syntax()
218 regs->reg61_qtable_base = mpp_buffer_get_fd(ctx->qp_table); in vdpu2_mpg4d_setup_regs_by_syntax()
230 hal_mpg4_ctx *ctx = (hal_mpg4_ctx *)hal; in vdpu2_mpg4d_init() local
259 ret = mpp_dev_init(&ctx->dev, VPU_CLIENT_VDPU2); in vdpu2_mpg4d_init()
265 ctx->frm_slots = cfg->frame_slots; in vdpu2_mpg4d_init()
266 ctx->pkt_slots = cfg->packet_slots; in vdpu2_mpg4d_init()
267 ctx->dec_cb = cfg->dec_cb; in vdpu2_mpg4d_init()
268 ctx->group = group; in vdpu2_mpg4d_init()
269 ctx->mv_buf = mv_buf; in vdpu2_mpg4d_init()
270 ctx->qp_table = qp_table; in vdpu2_mpg4d_init()
271 ctx->regs = regs; in vdpu2_mpg4d_init()
272 cfg->dev = ctx->dev; in vdpu2_mpg4d_init()
304 hal_mpg4_ctx *ctx = (hal_mpg4_ctx *)hal; in vdpu2_mpg4d_deinit() local
308 if (ctx->regs) { in vdpu2_mpg4d_deinit()
309 mpp_free(ctx->regs); in vdpu2_mpg4d_deinit()
310 ctx->regs = NULL; in vdpu2_mpg4d_deinit()
313 if (ctx->qp_table) { in vdpu2_mpg4d_deinit()
314 mpp_buffer_put(ctx->qp_table); in vdpu2_mpg4d_deinit()
315 ctx->qp_table = NULL; in vdpu2_mpg4d_deinit()
318 if (ctx->mv_buf) { in vdpu2_mpg4d_deinit()
319 mpp_buffer_put(ctx->mv_buf); in vdpu2_mpg4d_deinit()
320 ctx->mv_buf = NULL; in vdpu2_mpg4d_deinit()
323 if (ctx->group) { in vdpu2_mpg4d_deinit()
324 mpp_buffer_group_put(ctx->group); in vdpu2_mpg4d_deinit()
325 ctx->group = NULL; in vdpu2_mpg4d_deinit()
328 if (ctx->dev) { in vdpu2_mpg4d_deinit()
329 mpp_dev_deinit(ctx->dev); in vdpu2_mpg4d_deinit()
330 ctx->dev = NULL; in vdpu2_mpg4d_deinit()
339 hal_mpg4_ctx *ctx = (hal_mpg4_ctx *)hal; in vdpu2_mpg4d_gen_regs() local
345 M4vdVdpu2Regs_t *regs = ctx->regs; in vdpu2_mpg4d_gen_regs()
373 mpp_buf_slot_get_prop(ctx->pkt_slots, task->input, SLOT_BUFFER, &buf_pkt); in vdpu2_mpg4d_gen_regs()
375 vpu_mpg4d_get_buffer_by_index(ctx, task->output, &buf_frm_curr); in vdpu2_mpg4d_gen_regs()
376 vpu_mpg4d_get_buffer_by_index(ctx, task->refer[0], &buf_frm_ref0); in vdpu2_mpg4d_gen_regs()
377 vpu_mpg4d_get_buffer_by_index(ctx, task->refer[1], &buf_frm_ref1); in vdpu2_mpg4d_gen_regs()
380 ctx->fd_curr = mpp_buffer_get_fd(buf_frm_curr); in vdpu2_mpg4d_gen_regs()
381 ctx->fd_ref0 = (buf_frm_ref0) ? (mpp_buffer_get_fd(buf_frm_ref0)) : (-1); in vdpu2_mpg4d_gen_regs()
382 ctx->fd_ref1 = (buf_frm_ref1) ? (mpp_buffer_get_fd(buf_frm_ref1)) : (-1); in vdpu2_mpg4d_gen_regs()
383 regs->reg63_cur_pic_base = (RK_U32)ctx->fd_curr; in vdpu2_mpg4d_gen_regs()
387 vdpu2_mpg4d_setup_regs_by_syntax(ctx, task->syntax); in vdpu2_mpg4d_gen_regs()
391 RK_U32 strm_len = MPP_ALIGN(ctx->bitstrm_len, 16) + 64; in vdpu2_mpg4d_gen_regs()
392 memset(ptr + ctx->bitstrm_len, 0, strm_len - ctx->bitstrm_len); in vdpu2_mpg4d_gen_regs()
401 hal_mpg4_ctx *ctx = (hal_mpg4_ctx *)hal; in vdpu2_mpg4d_start() local
402 RK_U32* regs = (RK_U32 *)ctx->regs; in vdpu2_mpg4d_start()
422 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in vdpu2_mpg4d_start()
432 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg); in vdpu2_mpg4d_start()
438 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL); in vdpu2_mpg4d_start()
452 hal_mpg4_ctx *ctx = (hal_mpg4_ctx *)hal; in vdpu2_mpg4d_wait() local
453 M4vdVdpu2Regs_t *regs = (M4vdVdpu2Regs_t *)ctx->regs; in vdpu2_mpg4d_wait()
455 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL); in vdpu2_mpg4d_wait()
468 if (ctx->dec_cb) { in vdpu2_mpg4d_wait()
475 param.regs = (RK_U32 *)ctx->regs; in vdpu2_mpg4d_wait()
477 mpp_callback(ctx->dec_cb, ¶m); in vdpu2_mpg4d_wait()