Lines Matching refs:ctx
35 static void vdpu1_mpg4d_setup_regs_by_syntax(hal_mpg4_ctx *ctx, MppSyntax syntax) in vdpu1_mpg4d_setup_regs_by_syntax() argument
37 M4vdVdpu1Regs_t *regs = ctx->regs; in vdpu1_mpg4d_setup_regs_by_syntax()
41 RK_S32 mv_buf_fd = mpp_buffer_get_fd(ctx->mv_buf); in vdpu1_mpg4d_setup_regs_by_syntax()
58 ctx->bitstrm_len = stream_length; in vdpu1_mpg4d_setup_regs_by_syntax()
73 RK_U8 *dst = (RK_U8 *)mpp_buffer_get_ptr(ctx->qp_table); in vdpu1_mpg4d_setup_regs_by_syntax()
125 mpp_dev_set_reg_offset(ctx->dev, 12, consumed_bytes_align); in vdpu1_mpg4d_setup_regs_by_syntax()
145 mpp_assert(ctx->fd_ref1 >= 0); in vdpu1_mpg4d_setup_regs_by_syntax()
146 if (ctx->fd_ref1 >= 0) { in vdpu1_mpg4d_setup_regs_by_syntax()
147 regs->SwReg14.sw_refer0_base = (RK_U32)ctx->fd_ref1; in vdpu1_mpg4d_setup_regs_by_syntax()
148 regs->SwReg15.sw_refer1_base = (RK_U32)ctx->fd_ref1; in vdpu1_mpg4d_setup_regs_by_syntax()
150 regs->SwReg14.sw_refer0_base = (RK_U32)ctx->fd_curr; in vdpu1_mpg4d_setup_regs_by_syntax()
151 regs->SwReg15.sw_refer1_base = (RK_U32)ctx->fd_curr; in vdpu1_mpg4d_setup_regs_by_syntax()
154 mpp_assert(ctx->fd_ref0 >= 0); in vdpu1_mpg4d_setup_regs_by_syntax()
155 if (ctx->fd_ref0 >= 0) { in vdpu1_mpg4d_setup_regs_by_syntax()
156 regs->SwReg16.sw_refer2_base = (RK_U32)ctx->fd_ref0; in vdpu1_mpg4d_setup_regs_by_syntax()
157 regs->SwReg17.sw_refer3_base = (RK_U32)ctx->fd_ref0; in vdpu1_mpg4d_setup_regs_by_syntax()
159 regs->SwReg16.sw_refer2_base = (RK_U32)ctx->fd_curr; in vdpu1_mpg4d_setup_regs_by_syntax()
160 regs->SwReg17.sw_refer3_base = (RK_U32)ctx->fd_curr; in vdpu1_mpg4d_setup_regs_by_syntax()
177 if (ctx->fd_ref0 >= 0) { in vdpu1_mpg4d_setup_regs_by_syntax()
178 regs->SwReg14.sw_refer0_base = (RK_U32)ctx->fd_ref0; in vdpu1_mpg4d_setup_regs_by_syntax()
179 regs->SwReg15.sw_refer1_base = (RK_U32)ctx->fd_ref0; in vdpu1_mpg4d_setup_regs_by_syntax()
181 regs->SwReg14.sw_refer0_base = (RK_U32)ctx->fd_curr; in vdpu1_mpg4d_setup_regs_by_syntax()
182 regs->SwReg15.sw_refer1_base = (RK_U32)ctx->fd_curr; in vdpu1_mpg4d_setup_regs_by_syntax()
184 regs->SwReg16.sw_refer2_base = (RK_U32)ctx->fd_curr; in vdpu1_mpg4d_setup_regs_by_syntax()
185 regs->SwReg17.sw_refer3_base = (RK_U32)ctx->fd_curr; in vdpu1_mpg4d_setup_regs_by_syntax()
196 regs->SwReg14.sw_refer0_base = (RK_U32)ctx->fd_curr; in vdpu1_mpg4d_setup_regs_by_syntax()
197 regs->SwReg15.sw_refer1_base = (RK_U32)ctx->fd_curr; in vdpu1_mpg4d_setup_regs_by_syntax()
198 regs->SwReg16.sw_refer2_base = (RK_U32)ctx->fd_curr; in vdpu1_mpg4d_setup_regs_by_syntax()
199 regs->SwReg17.sw_refer3_base = (RK_U32)ctx->fd_curr; in vdpu1_mpg4d_setup_regs_by_syntax()
220 regs->SwReg40.sw_qtable_base = mpp_buffer_get_fd(ctx->qp_table); in vdpu1_mpg4d_setup_regs_by_syntax()
232 hal_mpg4_ctx *ctx = (hal_mpg4_ctx *)hal; in vdpu1_mpg4d_init() local
261 ret = mpp_dev_init(&ctx->dev, VPU_CLIENT_VDPU1); in vdpu1_mpg4d_init()
267 ctx->frm_slots = cfg->frame_slots; in vdpu1_mpg4d_init()
268 ctx->pkt_slots = cfg->packet_slots; in vdpu1_mpg4d_init()
269 ctx->dec_cb = cfg->dec_cb; in vdpu1_mpg4d_init()
270 ctx->group = group; in vdpu1_mpg4d_init()
271 ctx->mv_buf = mv_buf; in vdpu1_mpg4d_init()
272 ctx->qp_table = qp_table; in vdpu1_mpg4d_init()
273 ctx->regs = regs; in vdpu1_mpg4d_init()
274 cfg->dev = ctx->dev; in vdpu1_mpg4d_init()
306 hal_mpg4_ctx *ctx = (hal_mpg4_ctx *)hal; in vdpu1_mpg4d_deinit() local
310 if (ctx->regs) { in vdpu1_mpg4d_deinit()
311 mpp_free(ctx->regs); in vdpu1_mpg4d_deinit()
312 ctx->regs = NULL; in vdpu1_mpg4d_deinit()
315 if (ctx->qp_table) { in vdpu1_mpg4d_deinit()
316 mpp_buffer_put(ctx->qp_table); in vdpu1_mpg4d_deinit()
317 ctx->qp_table = NULL; in vdpu1_mpg4d_deinit()
320 if (ctx->mv_buf) { in vdpu1_mpg4d_deinit()
321 mpp_buffer_put(ctx->mv_buf); in vdpu1_mpg4d_deinit()
322 ctx->mv_buf = NULL; in vdpu1_mpg4d_deinit()
325 if (ctx->group) { in vdpu1_mpg4d_deinit()
326 mpp_buffer_group_put(ctx->group); in vdpu1_mpg4d_deinit()
327 ctx->group = NULL; in vdpu1_mpg4d_deinit()
330 if (ctx->dev) { in vdpu1_mpg4d_deinit()
331 mpp_dev_deinit(ctx->dev); in vdpu1_mpg4d_deinit()
332 ctx->dev = NULL; in vdpu1_mpg4d_deinit()
341 hal_mpg4_ctx *ctx = (hal_mpg4_ctx *)hal; in vdpu1_mpg4d_gen_regs() local
347 M4vdVdpu1Regs_t *regs = ctx->regs; in vdpu1_mpg4d_gen_regs()
375 mpp_buf_slot_get_prop(ctx->pkt_slots, task->input, SLOT_BUFFER, &buf_pkt); in vdpu1_mpg4d_gen_regs()
377 vpu_mpg4d_get_buffer_by_index(ctx, task->output, &buf_frm_curr); in vdpu1_mpg4d_gen_regs()
378 vpu_mpg4d_get_buffer_by_index(ctx, task->refer[0], &buf_frm_ref0); in vdpu1_mpg4d_gen_regs()
379 vpu_mpg4d_get_buffer_by_index(ctx, task->refer[1], &buf_frm_ref1); in vdpu1_mpg4d_gen_regs()
382 ctx->fd_curr = mpp_buffer_get_fd(buf_frm_curr); in vdpu1_mpg4d_gen_regs()
383 ctx->fd_ref0 = (buf_frm_ref0) ? (mpp_buffer_get_fd(buf_frm_ref0)) : (-1); in vdpu1_mpg4d_gen_regs()
384 ctx->fd_ref1 = (buf_frm_ref1) ? (mpp_buffer_get_fd(buf_frm_ref1)) : (-1); in vdpu1_mpg4d_gen_regs()
385 regs->SwReg13.dec_out_st_adr = (RK_U32)ctx->fd_curr; in vdpu1_mpg4d_gen_regs()
389 vdpu1_mpg4d_setup_regs_by_syntax(ctx, task->syntax); in vdpu1_mpg4d_gen_regs()
393 RK_U32 strm_len = MPP_ALIGN(ctx->bitstrm_len, 16) + 64; in vdpu1_mpg4d_gen_regs()
394 memset(ptr + ctx->bitstrm_len, 0, strm_len - ctx->bitstrm_len); in vdpu1_mpg4d_gen_regs()
403 hal_mpg4_ctx *ctx = (hal_mpg4_ctx *)hal; in vdpu1_mpg4d_start() local
404 RK_U32* regs = (RK_U32 *)ctx->regs; in vdpu1_mpg4d_start()
424 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in vdpu1_mpg4d_start()
434 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg); in vdpu1_mpg4d_start()
440 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL); in vdpu1_mpg4d_start()
454 hal_mpg4_ctx *ctx = (hal_mpg4_ctx *)hal; in vdpu1_mpg4d_wait() local
455 M4vdVdpu1Regs_t *regs = (M4vdVdpu1Regs_t *)ctx->regs; in vdpu1_mpg4d_wait()
457 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL); in vdpu1_mpg4d_wait()
469 if (ctx->dec_cb) { in vdpu1_mpg4d_wait()
473 param.regs = (RK_U32 *)ctx->regs; in vdpu1_mpg4d_wait()
476 mpp_callback(ctx->dec_cb, ¶m); in vdpu1_mpg4d_wait()