Lines Matching refs:val
293 RK_U32 *reg = ctx->regs_set.val; in setup_intra_refresh()
294 RK_U32 val = 0; in setup_intra_refresh() local
324 val = VEPU_REG_INTRA_AREA_TOP(top) in setup_intra_refresh()
328 H264E_HAL_SET_REG(reg, VEPU_REG_INTRA_AREA_CTRL, val); in setup_intra_refresh()
349 RK_U32 *reg = ctx->regs_set.val; in hal_h264e_vepu2_gen_regs_v2()
354 RK_U32 val = 0; in hal_h264e_vepu2_gen_regs_v2() local
389 val = VEPU_REG_AXI_CTRL_READ_ID(0); in hal_h264e_vepu2_gen_regs_v2()
390 val |= VEPU_REG_AXI_CTRL_WRITE_ID(0); in hal_h264e_vepu2_gen_regs_v2()
391 val |= VEPU_REG_AXI_CTRL_BURST_LEN(16); in hal_h264e_vepu2_gen_regs_v2()
392 val |= VEPU_REG_AXI_CTRL_INCREMENT_MODE(0); in hal_h264e_vepu2_gen_regs_v2()
393 val |= VEPU_REG_AXI_CTRL_BIRST_DISCARD(0); in hal_h264e_vepu2_gen_regs_v2()
394 H264E_HAL_SET_REG(reg, VEPU_REG_AXI_CTRL, val); in hal_h264e_vepu2_gen_regs_v2()
399 val = 0; in hal_h264e_vepu2_gen_regs_v2()
401 val = VEPU_REG_DISABLE_QUARTER_PIXEL_MV; in hal_h264e_vepu2_gen_regs_v2()
402 val |= VEPU_REG_CABAC_INIT_IDC(slice->cabac_init_idc); in hal_h264e_vepu2_gen_regs_v2()
404 val |= VEPU_REG_ENTROPY_CODING_MODE; in hal_h264e_vepu2_gen_regs_v2()
406 val |= VEPU_REG_H264_TRANS8X8_MODE; in hal_h264e_vepu2_gen_regs_v2()
408 val |= VEPU_REG_H264_INTER4X4_MODE; in hal_h264e_vepu2_gen_regs_v2()
410 val |= VEPU_REG_H264_SLICE_SIZE(hw_mbrc->slice_size_mb_rows); in hal_h264e_vepu2_gen_regs_v2()
411 H264E_HAL_SET_REG(reg, VEPU_REG_ENC_CTRL0, val); in hal_h264e_vepu2_gen_regs_v2()
423 val = VEPU_REG_STREAM_START_OFFSET(first_free_bit) | in hal_h264e_vepu2_gen_regs_v2()
427 H264E_HAL_SET_REG(reg, VEPU_REG_ENC_OVER_FILL_STRM_OFFSET, val); in hal_h264e_vepu2_gen_regs_v2()
430 val = VEPU_REG_IN_IMG_CHROMA_OFFSET(0) in hal_h264e_vepu2_gen_regs_v2()
434 H264E_HAL_SET_REG(reg, VEPU_REG_INPUT_LUMA_INFO, val); in hal_h264e_vepu2_gen_regs_v2()
436 val = VEPU_REG_CHECKPOINT_CHECK1(hw_mbrc->cp_target[0]) in hal_h264e_vepu2_gen_regs_v2()
438 H264E_HAL_SET_REG(reg, VEPU_REG_CHECKPOINT(0), val); in hal_h264e_vepu2_gen_regs_v2()
440 val = VEPU_REG_CHECKPOINT_CHECK1(hw_mbrc->cp_target[2]) in hal_h264e_vepu2_gen_regs_v2()
442 H264E_HAL_SET_REG(reg, VEPU_REG_CHECKPOINT(1), val); in hal_h264e_vepu2_gen_regs_v2()
444 val = VEPU_REG_CHECKPOINT_CHECK1(hw_mbrc->cp_target[4]) in hal_h264e_vepu2_gen_regs_v2()
446 H264E_HAL_SET_REG(reg, VEPU_REG_CHECKPOINT(2), val); in hal_h264e_vepu2_gen_regs_v2()
448 val = VEPU_REG_CHECKPOINT_CHECK1(hw_mbrc->cp_target[6]) in hal_h264e_vepu2_gen_regs_v2()
450 H264E_HAL_SET_REG(reg, VEPU_REG_CHECKPOINT(3), val); in hal_h264e_vepu2_gen_regs_v2()
452 val = VEPU_REG_CHECKPOINT_CHECK1(hw_mbrc->cp_target[8]) in hal_h264e_vepu2_gen_regs_v2()
454 H264E_HAL_SET_REG(reg, VEPU_REG_CHECKPOINT(4), val); in hal_h264e_vepu2_gen_regs_v2()
456 val = VEPU_REG_CHKPT_WORD_ERR_CHK1(hw_mbrc->cp_error[0]) in hal_h264e_vepu2_gen_regs_v2()
458 H264E_HAL_SET_REG(reg, VEPU_REG_CHKPT_WORD_ERR(0), val); in hal_h264e_vepu2_gen_regs_v2()
460 val = VEPU_REG_CHKPT_WORD_ERR_CHK1(hw_mbrc->cp_error[2]) in hal_h264e_vepu2_gen_regs_v2()
462 H264E_HAL_SET_REG(reg, VEPU_REG_CHKPT_WORD_ERR(1), val); in hal_h264e_vepu2_gen_regs_v2()
464 val = VEPU_REG_CHKPT_WORD_ERR_CHK1(hw_mbrc->cp_error[4]) in hal_h264e_vepu2_gen_regs_v2()
466 H264E_HAL_SET_REG(reg, VEPU_REG_CHKPT_WORD_ERR(2), val); in hal_h264e_vepu2_gen_regs_v2()
468 val = VEPU_REG_CHKPT_DELTA_QP_CHK6(hw_mbrc->cp_delta_qp[6]) in hal_h264e_vepu2_gen_regs_v2()
475 H264E_HAL_SET_REG(reg, VEPU_REG_CHKPT_DELTA_QP, val); in hal_h264e_vepu2_gen_regs_v2()
477 val = VEPU_REG_MAD_THRESHOLD(hw_mbrc->mad_threshold) in hal_h264e_vepu2_gen_regs_v2()
481 H264E_HAL_SET_REG(reg, VEPU_REG_ENC_CTRL1, val); in hal_h264e_vepu2_gen_regs_v2()
483 val = VEPU_REG_INTRA16X16_MODE(h264_intra16_favor[hw_mbrc->qp_init]) in hal_h264e_vepu2_gen_regs_v2()
485 H264E_HAL_SET_REG(reg, VEPU_REG_INTRA_INTER_MODE, val); in hal_h264e_vepu2_gen_regs_v2()
487 val = VEPU_REG_PPS_INIT_QP(pps->pic_init_qp) in hal_h264e_vepu2_gen_regs_v2()
494 val |= VEPU_REG_FILTER_DISABLE; in hal_h264e_vepu2_gen_regs_v2()
497 val |= VEPU_REG_CONSTRAINED_INTRA_PREDICTION; in hal_h264e_vepu2_gen_regs_v2()
498 H264E_HAL_SET_REG(reg, VEPU_REG_ENC_CTRL2, val); in hal_h264e_vepu2_gen_regs_v2()
508 val = VEPU_REG_ROI1_TOP_MB(mb_h) in hal_h264e_vepu2_gen_regs_v2()
512 H264E_HAL_SET_REG(reg, VEPU_REG_ROI1, val); in hal_h264e_vepu2_gen_regs_v2()
514 val = VEPU_REG_ROI2_TOP_MB(mb_h) in hal_h264e_vepu2_gen_regs_v2()
518 H264E_HAL_SET_REG(reg, VEPU_REG_ROI2, val); in hal_h264e_vepu2_gen_regs_v2()
521 val = VEPU_REG_RGB2YUV_CONVERSION_COEFB(hw_prep->color_conversion_coeff_b) in hal_h264e_vepu2_gen_regs_v2()
523 H264E_HAL_SET_REG(reg, VEPU_REG_RGB2YUV_CONVERSION_COEF1, val); in hal_h264e_vepu2_gen_regs_v2()
525 val = VEPU_REG_RGB2YUV_CONVERSION_COEFE(hw_prep->color_conversion_coeff_e) in hal_h264e_vepu2_gen_regs_v2()
527 H264E_HAL_SET_REG(reg, VEPU_REG_RGB2YUV_CONVERSION_COEF2, val); in hal_h264e_vepu2_gen_regs_v2()
529 val = VEPU_REG_RGB2YUV_CONVERSION_COEFF(hw_prep->color_conversion_coeff_f); in hal_h264e_vepu2_gen_regs_v2()
530 H264E_HAL_SET_REG(reg, VEPU_REG_RGB2YUV_CONVERSION_COEF3, val); in hal_h264e_vepu2_gen_regs_v2()
532 val = VEPU_REG_RGB_MASK_B_MSB(hw_prep->b_mask_msb) in hal_h264e_vepu2_gen_regs_v2()
535 H264E_HAL_SET_REG(reg, VEPU_REG_RGB_MASK_MSB, val); //FIXED in hal_h264e_vepu2_gen_regs_v2()
543 val = VEPU_REG_1MV_PENALTY(diff_mv_penalty[1]) in hal_h264e_vepu2_gen_regs_v2()
548 val |= VEPU_REG_SPLIT_MV_MODE_EN; in hal_h264e_vepu2_gen_regs_v2()
549 H264E_HAL_SET_REG(reg, VEPU_REG_MV_PENALTY, val); in hal_h264e_vepu2_gen_regs_v2()
551 val = VEPU_REG_H264_LUMA_INIT_QP(hw_mbrc->qp_init) in hal_h264e_vepu2_gen_regs_v2()
555 H264E_HAL_SET_REG(reg, VEPU_REG_QP_VAL, val); in hal_h264e_vepu2_gen_regs_v2()
557 val = VEPU_REG_ZERO_MV_FAVOR_D2(10); in hal_h264e_vepu2_gen_regs_v2()
558 H264E_HAL_SET_REG(reg, VEPU_REG_MVC_RELATE, val); in hal_h264e_vepu2_gen_regs_v2()
560 val = VEPU_REG_OUTPUT_SWAP32 in hal_h264e_vepu2_gen_regs_v2()
566 H264E_HAL_SET_REG(reg, VEPU_REG_DATA_ENDIAN, val); in hal_h264e_vepu2_gen_regs_v2()
568 val = VEPU_REG_PPS_ID(pps->pps_id) in hal_h264e_vepu2_gen_regs_v2()
571 H264E_HAL_SET_REG(reg, VEPU_REG_ENC_CTRL3, val); in hal_h264e_vepu2_gen_regs_v2()
573 val = VEPU_REG_INTERRUPT_TIMEOUT_EN; in hal_h264e_vepu2_gen_regs_v2()
574 H264E_HAL_SET_REG(reg, VEPU_REG_INTERRUPT, val); in hal_h264e_vepu2_gen_regs_v2()
586 val = VEPU_REG_DMV_PENALTY_TABLE_BIT(dmv_penalty[i], 3); in hal_h264e_vepu2_gen_regs_v2()
587 val |= VEPU_REG_DMV_PENALTY_TABLE_BIT(dmv_penalty[i + 1], 2); in hal_h264e_vepu2_gen_regs_v2()
588 val |= VEPU_REG_DMV_PENALTY_TABLE_BIT(dmv_penalty[i + 2], 1); in hal_h264e_vepu2_gen_regs_v2()
589 val |= VEPU_REG_DMV_PENALTY_TABLE_BIT(dmv_penalty[i + 3], 0); in hal_h264e_vepu2_gen_regs_v2()
590 H264E_HAL_SET_REG(reg, VEPU_REG_DMV_PENALTY_TBL(i / 4), val); in hal_h264e_vepu2_gen_regs_v2()
592 val = VEPU_REG_DMV_Q_PIXEL_PENALTY_TABLE_BIT( in hal_h264e_vepu2_gen_regs_v2()
594 val |= VEPU_REG_DMV_Q_PIXEL_PENALTY_TABLE_BIT( in hal_h264e_vepu2_gen_regs_v2()
596 val |= VEPU_REG_DMV_Q_PIXEL_PENALTY_TABLE_BIT( in hal_h264e_vepu2_gen_regs_v2()
598 val |= VEPU_REG_DMV_Q_PIXEL_PENALTY_TABLE_BIT( in hal_h264e_vepu2_gen_regs_v2()
600 H264E_HAL_SET_REG(reg, VEPU_REG_DMV_Q_PIXEL_PENALTY_TBL(i / 4), val); in hal_h264e_vepu2_gen_regs_v2()
631 val = VEPU_REG_MB_HEIGHT(mb_h) in hal_h264e_vepu2_gen_regs_v2()
636 H264E_HAL_SET_REG(reg, VEPU_REG_ENCODE_START, val); in hal_h264e_vepu2_gen_regs_v2()
698 RK_U32 *reg_val = reg->val; in h264e_vepu2_get_mbrc()