1475     size_t context_update_tile_id =  dxva->tiles.context_update_id;  in vdpu_av1d_set_tile_info_regs()
1476     size_t context_update_y = context_update_tile_id / dxva->tiles.cols;  in vdpu_av1d_set_tile_info_regs()
1477     size_t context_update_x = context_update_tile_id % dxva->tiles.cols;  in vdpu_av1d_set_tile_info_regs()
1482             context_update_x * dxva->tiles.rows + context_update_y;  in vdpu_av1d_set_tile_info_regs()
1484     regs->swreg10.sw_tile_enable = (dxva->tiles.cols > 1) || (dxva->tiles.rows > 1);  in vdpu_av1d_set_tile_info_regs()
1485     regs->swreg10.sw_num_tile_cols_8k       = dxva->tiles.cols;  in vdpu_av1d_set_tile_info_regs()
1486     regs->swreg10.sw_num_tile_rows_8k_av1   = dxva->tiles.rows;  in vdpu_av1d_set_tile_info_regs()
1489     regs->swreg11.sw_dec_tile_size_mag      = dxva->tiles.tile_sz_mag;  in vdpu_av1d_set_tile_info_regs()
1528     RK_S32 size0 = transpose ?  dxva->tiles.cols : dxva->tiles.rows;  in vdpu_av1d_set_tile_info_mem()
1529     RK_S32 size1 = transpose ? dxva->tiles.rows  :  dxva->tiles.cols;  in vdpu_av1d_set_tile_info_mem()
1532     RK_U32 tiles[2][64];  in vdpu_av1d_set_tile_info_mem()  local
1538         for (i = 0; i < dxva->tiles.cols; i++) {  in vdpu_av1d_set_tile_info_mem()
1539             tiles[0][i] = val;  in vdpu_av1d_set_tile_info_mem()
1540             val += dxva->tiles.widths[i];  in vdpu_av1d_set_tile_info_mem()
1542         tiles[0][i] = val;  in vdpu_av1d_set_tile_info_mem()
1545         for (i = 0; i < dxva->tiles.rows; i++) {  in vdpu_av1d_set_tile_info_mem()
1546             tiles[1][i] = val;  in vdpu_av1d_set_tile_info_mem()
1547             val += dxva->tiles.heights[i];  in vdpu_av1d_set_tile_info_mem()
1549         tiles[1][i] = val;  in vdpu_av1d_set_tile_info_mem()
1560             RK_U32 y0 = tiles[1][tile_y];  in vdpu_av1d_set_tile_info_mem()
1561             RK_U32 y1 = tiles[1][tile_y + 1];  in vdpu_av1d_set_tile_info_mem()
1562             RK_U32 x0 = tiles[0][tile_x];  in vdpu_av1d_set_tile_info_mem()
1563             RK_U32 x1 = tiles[0][tile_x + 1];  in vdpu_av1d_set_tile_info_mem()
1565             RK_U8 leftmost = (tile_x == dxva->tiles.cols - 1);  in vdpu_av1d_set_tile_info_mem()
1583             start = dxva->tiles.tile_offset_start[tile_id];  in vdpu_av1d_set_tile_info_mem()
1594             end = dxva->tiles.tile_offset_end[tile_id];  in vdpu_av1d_set_tile_info_mem()