1095     regs->swreg5.sw_ref_scaling_enable = ref_scale_e;  in vdpu_av1d_set_reference_frames()
1204     regs->swreg5.sw_superres_is_scaled = superres_is_scaled;  in vdpu_av1d_superres_params()
1243     regs->swreg5.sw_error_resilient     =  dxva->coding.error_resilient_mode;  in vdpu_av1d_set_segmentation()
1246         || regs->swreg5.sw_error_resilient) {  in vdpu_av1d_set_segmentation()
1316     regs->swreg5.sw_preskip_segid   = preskip_segid;  in vdpu_av1d_set_segmentation()
1398     regs->swreg5.sw_filt_level_base_gt32    = dxva->loop_filter.filter_level[0] > 32;  in vdpu_av1d_set_loopfilter()
1942     regs->swreg5.sw_tempor_mvp_e        = dxva->coding.use_ref_frame_mvs;  in vdpu_av1d_gen_regs()
1943     regs->swreg5.sw_delta_lf_res_log    = dxva->loop_filter.delta_lf_res;  in vdpu_av1d_gen_regs()
1944     regs->swreg5.sw_delta_lf_multi      = dxva->loop_filter.delta_lf_multi;  in vdpu_av1d_gen_regs()
1945     regs->swreg5.sw_delta_lf_present    = dxva->loop_filter.delta_lf_present;  in vdpu_av1d_gen_regs()
1946     regs->swreg5.sw_disable_cdf_update  = dxva->coding.disable_cdf_update;  in vdpu_av1d_gen_regs()
1947     regs->swreg5.sw_allow_warp          = dxva->coding.warped_motion;  in vdpu_av1d_gen_regs()
1948     regs->swreg5.sw_show_frame          = dxva->format.show_frame;  in vdpu_av1d_gen_regs()
1949     regs->swreg5.sw_switchable_motion_mode  = dxva->coding.switchable_motion_mode;  in vdpu_av1d_gen_regs()
1950     regs->swreg5.sw_enable_cdef         = !(dxva->cdef.bits == 0 && dxva->cdef.damping == 0 &&  in vdpu_av1d_gen_regs()
1955     regs->swreg5.sw_allow_masked_compound   = dxva->coding.masked_compound;  in vdpu_av1d_gen_regs()
1956     regs->swreg5.sw_allow_interintra    = dxva->coding.interintra_compound;  in vdpu_av1d_gen_regs()
1957     regs->swreg5.sw_enable_intra_edge_filter = dxva->coding.intra_edge_filter;  in vdpu_av1d_gen_regs()
1958     regs->swreg5.sw_allow_filter_intra  = dxva->coding.filter_intra;  in vdpu_av1d_gen_regs()
1959     regs->swreg5.sw_enable_jnt_comp     = dxva->coding.jnt_comp;  in vdpu_av1d_gen_regs()
1960     regs->swreg5.sw_enable_dual_filter  = dxva->coding.dual_filter;  in vdpu_av1d_gen_regs()
1961     regs->swreg5.sw_reduced_tx_set_used = dxva->coding.reduced_tx_set;  in vdpu_av1d_gen_regs()
1962     regs->swreg5.sw_allow_screen_content_tools = dxva->coding.screen_content_tools;  in vdpu_av1d_gen_regs()
1963     regs->swreg5.sw_allow_intrabc       = dxva->coding.intrabc;  in vdpu_av1d_gen_regs()
1965     regs->swreg5.sw_force_interger_mv   = dxva->coding.integer_mv;  in vdpu_av1d_gen_regs()
2126 …      regs->swreg5.sw_strm_start_bit    =  (dxva->frame_tag_size & 0xf) * 8; // bit start to decode  in vdpu_av1d_gen_regs()
2136         AV1D_DBG(AV1D_DBG_LOG, "stream start_bit %d\n", regs->swreg5.sw_strm_start_bit);  in vdpu_av1d_gen_regs()
2172         RK_U32 bypass_filter = !regs->swreg5.sw_superres_is_scaled &&  in vdpu_av1d_gen_regs()
2173                                !regs->swreg5.sw_enable_cdef &&  in vdpu_av1d_gen_regs()