1016         regs->swreg11.sw_use_temporal0_mvs = 0;  in vdpu_av1d_set_reference_frames()
1017         regs->swreg11.sw_use_temporal1_mvs = 0;  in vdpu_av1d_set_reference_frames()
1018         regs->swreg11.sw_use_temporal2_mvs = 0;  in vdpu_av1d_set_reference_frames()
1019         regs->swreg11.sw_use_temporal3_mvs = 0;  in vdpu_av1d_set_reference_frames()
1024             regs->swreg11.sw_use_temporal0_mvs = 1;  in vdpu_av1d_set_reference_frames()
1031             regs->swreg11.sw_use_temporal1_mvs = 1;  in vdpu_av1d_set_reference_frames()
1038             regs->swreg11.sw_use_temporal2_mvs = 1;  in vdpu_av1d_set_reference_frames()
1059                 regs->swreg11.sw_use_temporal3_mvs = 1;  in vdpu_av1d_set_reference_frames()
1247         regs->swreg11.sw_use_temporal3_mvs = 0;  in vdpu_av1d_set_segmentation()
1479     regs->swreg11.sw_multicore_expect_context_update = (0 == context_update_x);  in vdpu_av1d_set_tile_info_regs()
1489     regs->swreg11.sw_dec_tile_size_mag      = dxva->tiles.tile_sz_mag;  in vdpu_av1d_set_tile_info_regs()
2067     regs->swreg11.sw_mcomp_filt_type    = dxva->interp_filter;  in vdpu_av1d_gen_regs()
2068     regs->swreg11.sw_high_prec_mv_e     = dxva->coding.high_precision_mv;  in vdpu_av1d_gen_regs()
2069     regs->swreg11.sw_comp_pred_mode     = dxva->coding.reference_mode ? 2 : 0;  in vdpu_av1d_gen_regs()
2070     regs->swreg11.sw_transform_mode     = dxva->coding.tx_mode ? (dxva->coding.tx_mode + 2) : 0;  in vdpu_av1d_gen_regs()