812         RK_U32 ref = i - 1;  in vdpu_av1d_set_reference_frames()  local
819             tmp1 =  dxva->frame_refs[ref].width;  in vdpu_av1d_set_reference_frames()
820             tmp2 =  dxva->frame_refs[ref].height;  in vdpu_av1d_set_reference_frames()
821             if (dxva->frame_refs[ref].Index > 0) {  in vdpu_av1d_set_reference_frames()
822                 idx = dxva->frame_refs[ref].Index;  in vdpu_av1d_set_reference_frames()
826         set_ref_width(regs, ref, tmp1);  in vdpu_av1d_set_reference_frames()
827         set_ref_height(regs, ref, tmp2);  in vdpu_av1d_set_reference_frames()
831         set_ref_hor_scale(regs, ref, tmp1);  in vdpu_av1d_set_reference_frames()
832         set_ref_ver_scale(regs, ref, tmp2);  in vdpu_av1d_set_reference_frames()
842         set_ref_lum_base(regs, ref, idx, ctx->tile_out_bufs);  in vdpu_av1d_set_reference_frames()
843         set_ref_cb_base(p_hal,  ref, idx, ctx->tile_out_bufs, y_stride);  in vdpu_av1d_set_reference_frames()
844         set_ref_dbase  (p_hal,  ref, idx, ctx->tile_out_bufs, mv_offset);  in vdpu_av1d_set_reference_frames()
846         set_ref_lum_base_msb(regs, ref, 0);  in vdpu_av1d_set_reference_frames()
847         set_ref_cb_base_msb(regs,  ref, 0);  in vdpu_av1d_set_reference_frames()
848         set_ref_dbase_msb  (regs,  ref, 0);  in vdpu_av1d_set_reference_frames()
851             set_ref_ty_base(regs,  ref, idx, ctx->tile_out_bufs);  in vdpu_av1d_set_reference_frames()
852             set_ref_tc_base(regs,  ref, idx, ctx->tile_out_bufs);  in vdpu_av1d_set_reference_frames()
853             set_ref_ty_base_msb(regs,  ref, 0);  in vdpu_av1d_set_reference_frames()
854             set_ref_tc_base_msb(regs,  ref, 0);  in vdpu_av1d_set_reference_frames()
856         set_ref_sign_bias(regs, ref, ctx->ref_frame_sign_bias[i]);  in vdpu_av1d_set_reference_frames()